On the Detection of Delay Faults. - Ankan K. Pramanick; Sudhakar M. Reddy (ITC, 1988)

On the computation of the ranges of detected delay fault sizes. - Ankan K. Pramanick; Sudhakar M. Reddy (ICCAD, 1989)

On the fault coverage of delay fault detecting tests. - Ankan K. Pramanick; Sudhakar M. Reddy (EURO-DAC, 1990)

On the design of path delay fault testable combinational circuits. - Ankan K. Pramanick; Sudhakar M. Reddy (FTCS, 1990)

On Multiple Path Propagating Tests for Path Delay Faults. - Ankan K. Pramanick; Sudhakar M. Reddy (ITC, 1991)

Design of Scan-Based Path-Delay-Testable Sequential Circuits. - Ankan K. Pramanick; Sandip Kundu (ITC, 1993)

On Unified Delay Fault Testing. - Ankan K. Pramanick; Sudhakar M. Reddy (VLSI Design, 1993)

Testability preserving Boolean transforms for logic synthesis. - Sandip Kundu; Ankan K. Pramanick (VTS, 1993)

Distributed Solutions to the Delay Fault Test Quality Evaluation Problem. - Ira Pramanick; Ankan K. Pramanick (HPDC, 1994)

Parallel Delay Fault Coverage and Test Quality Evaluation. - Ira Pramanick; Ankan K. Pramanick (ITC, 1995)

Efficient multiple path propagating tests for delay faults. - Ankan K. Pramanick; Sudhakar M. Reddy (J. Electron. Test., 1995)

On the fault coverage of gate delay fault detecting tests. - Ankan K. Pramanick; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Software development for an open architecture test system. - Bruce R. Parnas; Ankan K. Pramanick; Mark Elston; Toshiaki Adachi (ETS, 2004)

Test Programming Environment in a Modular, Open Architecture Test System. - Ankan K. Pramanick; Ramachandran Krishnaswamy; Mark Elston; Toshiaki Adachi; Harsanjeet Singh; Bruce R. Parnas (ITC, 2004)

Parallel, multi-DUT testing in an open architecture test system. - Toshiaki Adachi; Ankan K. Pramanick; Mark Elston (ITC, 2005)