A 4mW 1 GS/s continuous-time ΔΣ modulator with 15.6MHz bandwidth and 67 dB dynamic range. - Ankesh Jain; Muthusubramanian Venkateswaran; Shanthi Pavan (ESSCIRC, 2011)

Analysis and Design of a High Speed Continuous-time ΔΣ Modulator Using the Assisted Opamp Technique. - Ankesh Jain; Muthusubramaniam Venkatesan; Shanthi Pavan (IEEE J. Solid State Circuits, 2012)

Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface. - Ankesh Jain; Shanthi Pavan (ISCAS, 2013)

Characterization Techniques for High Speed Oversampled Data Converters. - Ankesh Jain; Shanthi Pavan (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback. - Ankesh Jain; Shanthi Pavan (VLSI Circuits, 2016)

An Efficient Self-Routing and Non-Blocking Interconnection Network on Chip. - Tripti Jain; Klaus Schneider 001; Ankesh Jain (NoCArc@MICRO, 2017)

Deriving concentrators from binary sorters using half cleaners. - Tripti Jain; Klaus Schneider 001; Ankesh Jain (ReConFig, 2017)

Interferer Induced Jitter Reduction in Bandpass CT ΣΔ Modulators for Receiver Applications. - Jiazuo Chi; Ankesh Jain; Jens Sauerbrey; Joachim Becker; Maurits Ortmanns (ISCAS, 2018)

Gain Mismatch Insensitive Time-Interleaved DAC for CT Delta Sigma Modulator by application of a Three-State DAC. - Ankesh Jain; Maurits Ortmanns (ISCAS, 2018)

A High-Resolution Delta-Sigma D/A Converter Architecture with High Tolerance to DAC Mismatch. - Yanquan Luo; Liang Qi 002; Ankesh Jain; Maurits Ortmanns (ISCAS, 2018)

A 0.4-V Gm-C Proportional-Integrator-Based Continuous-Time ΔΣ Modulator With 50-kHz BW and 74.4-dB SNDR. - Lishan Lv; Ankesh Jain; Xiong Zhou; Joachim Becker; Qiang Li 021; Maurits Ortmanns (IEEE J. Solid State Circuits, 2018)

Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback. - Ankesh Jain; Shanthi Pavan (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An Integrated Readout for Current Sensing based on a Σ∆ Modulator with Switched Capacitor Feedback. - Mahdi Rajabzadeh; Matthias Häberle; Ankesh Jain; Maurits Ortmanns (ESSCIRC, 2019)

Effective Filtering of Requantization Error in Dual Quantized CTDSM using FIR DAC. - Ankesh Jain; Ahmed Abdelaal; Maurits Ortmanns (ISCAS, 2019)

A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS. - Liang Qi 002; Ankesh Jain; Dongyang Jiang; Sai-Weng Sin; Rui Paulo Martins; Maurits Ortmanns (ISSCC, 2019)

Input Referred Comparator Noise in SAR ADCs. - Yanquan Luo; Ankesh Jain; Johannes Wagner 003; Maurits Ortmanns (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Reduction of the Weight-Decay Rate of Volatile Memory Synapses in an Analog Hardware Neural Network for Accurate and Scalable On-Chip Learning. - Janak Sharda; Nilabjo Dey; Ankesh Jain; Debanjan Bhowmik (ICONS, 2020)

System Level Modeling and Optimization of Hybrid Vibration Energy Harvesters. - Mounika Kundurthi; Dhiman Mallick; Ankesh Jain (ISCAS, 2020)

A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance. - Liang Qi 002; Ankesh Jain; Dongyang Jiang; Sai-Weng Sin; Rui Paulo Martins; Maurits Ortmanns (IEEE J. Solid State Circuits, 2020)

High speed Continuous-time Delta Sigma Modulators for Wide-band Applications: A review paper. - Ankesh Jain (ISOCC, 2021)

Electrical Energy Injection using Hybrid SECE for High Performance Nonlinear Mechanical Energy Harvesting. - Jatin Sharma; Pratibha Verma; Dhiman Mallick; Ankesh Jain (MWSCAS, 2021)

Modified Gm-Free Assisted Opamp Technique in Continuous Time Delta Sigma Modulators. - Sayan Banerjee; Ankesh Jain (APCCAS, 2023)

Graph of Circuits with GNN for Exploring the Optimal Design Space. - Aditya Hemant Shahane; Saripilli Swapna Manjiri; Ankesh Jain; Sandeep Kumar 005 (NeurIPS, 2023)

Analysis and Design of High-Speed, Linear and Fullscale Input Swing Voltage to Time Converters. - Shivani; Ankesh Jain (PRIME, 2024)

Hybrid Piezoelectric-Triboelectric Biomechanical Harvesting System for Wearable Applications. - Pratibha Verma; Sourav Naval; Dhiman Mallick; Ankesh Jain (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Analysis and Design Considerations for MASH of Noise Shaped SAR ADCs. - R. Arundeepakvel; Ankesh Jain (VLSID, 2025)

ΔΣ Modulators Employing MASH DSM DAC-Based Dual Quantization. - Ahmed Abdelaal; Michael Pietzko; John G. Kauffman; Ankesh Jain; Maurits Ortmanns (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)