Poster Abstract: Slot-Level Time-Triggered Scheduling on COTS Multicore Platform with Resource Contentions. - Ankit Agrawal 005; Gerhard Fohler; Jan Nowotsch; Sascha Uhrig; Michael Paulitsch (RTAS, 2016)

Contention-Aware Dynamic Memory Bandwidth Isolation with Predictability in COTS Multicores: An Avionics Case Study. - Ankit Agrawal 005; Gerhard Fohler; Johannes Freitag; Jan Nowotsch; Sascha Uhrig; Michael Paulitsch (ECRTS, 2017)

DRAM-related challenges in task scheduling with timing predictability on COTS multi-cores for safety-critical systems. - Ankit Agrawal 005; Gerhard Fohler (MEMSYS, 2017)

Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems. - Ankit Agrawal 005; Renato Mancuso 001; Rodolfo Pellizzoni; Gerhard Fohler (RTSS, 2018)

Hardware Contention-Aware Real-Time Scheduling on Multi-Core Platforms in Safety-Critical Systems. - Ankit Agrawal 005 (2019)