A trace signal selection algorithm for improved post-silicon debug. - Binod Kumar 001; Ankit Jindal; Virendra Singh (EWDTS, 2016)

Combining Restorability and Error Detection Ability for Effective Trace Signal Selection. - Binod Kumar 001; Ankit Jindal; Masahiro Fujita; Virendra Singh (ACM Great Lakes Symposium on VLSI, 2017)

Revisiting random access scan for effective enhancement of post-silicon observability. - Binod Kumar 001; Ankit Jindal; Jaynarayan T. Tudu; Brajesh Pandey; Virendra Singh (IOLTS, 2017)

Post-silicon observability enhancement with topology based trace signal selection. - Binod Kumar 001; Ankit Jindal; Masahiro Fujita; Virendra Singh (LATS, 2017)

A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection. - Binod Kumar 001; Kanad Basu; Ankit Jindal; Brajesh Pandey; Masahiro Fujita (VDAT, 2017)

Improving post-silicon error detection with topological selection of trace signals. - Binod Kumar 001; Kanad Basu; Ankit Jindal; Masahiro Fujita; Virendra Singh (VLSI-SoC, 2017)

A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. - Binod Kumar 001; Ankit Jindal; Virendra Singh; Masahiro Fujita (VLSID, 2017)

Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. - Ankit Jindal; Binod Kumar 001; Nitish Jindal; Masahiro Fujita; Virendra Singh (ISVLSI, 2018)

ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis. - Ankit Jindal; Binod Kumar 001; Kanad Basu; Masahiro Fujita (VLSID, 2018)