A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration. - Rakshith Saligram; Ankit Kaul; Muhannad S. Bakir; Arijit Raychowdhury (VLSI-SOC, 2020)

Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication. - Rakshith Saligram; Ankit Kaul; Muhannad S. Bakir; Arijit Raychowdhury (VLSI-SoC (Selected Papers), 2020)

Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance. - Ankit Kaul; Yandong Luo; Xiaochen Peng; Shimeng Yu; Muhannad S. Bakir (3DIC, 2021)

Electrical and Performance Benefits of Advanced Monolithic Cooling for 2.5D Heterogeneous ICs. - Sreejith Kochupurackal Rajan; Ankit Kaul; Gary S. May; Muhannad S. Bakir (3DIC, 2021)

Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture. - Lingjun Zhu; Tuan Ta; Rossana Liu; Rahul Mathur; Xiaoqing Xu; Shidhartha Das; Ankit Kaul; Alejandro Rico; Doug Joseph; Brian Cline; Sung Kyu Lim (ISLPED, 2021)

A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect. - Yandong Luo; Sourav Dutta; Ankit Kaul; Sung Kyu Lim; Muhannad S. Bakir; Suman Datta; Shimeng Yu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Methodologies for Modeling and Optimization of 2.5-D and 3-D Integration Architectures for Compute-In-Memory Applications. - Ankit Kaul (2023)

H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention. - Wantong Li; Madison Manley; James Read; Ankit Kaul; Muhannad S. Bakir; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory Accelerators. - Ankit Kaul; Madison Manley; James Read; Yandong Luo; Xiaochen Peng; Shimeng Yu; Muhannad S. Bakir (VLSI Technology and Circuits, 2024)