Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times. - Haralampos-G. D. Stratigopoulos; Manuel J. Barragán; Salvador Mir; Hervé Le Gall; Neha Bhargava; Ankur Bal (ITC, 2015)

Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques. - Manuel J. Barragán; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Le Gall; Neha Bhargava; Ankur Bal (IEEE Des. Test, 2016)

A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC. - Manuel J. Barragán; Rshdee Alhakim; Haralampos-G. D. Stratigopoulos; Matthieu Dubois; Salvador Mir; Hervé Le Gall; Neha Bhargava; Ankur Bal (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A Real Time Multi-Bit DAC Mismatch Estimation & Correction Technique For Wideband Continuous Time Sigma Delta Modulators. - Ankur Bal; Sharad Gupta; Rupesh Singh (VLSID, 2022)

A Low-Cost 0.00063-mm2, 0.44-pJ/b, 2-Gb/s All-Digital Fully Synthesizable CDR for Serial Links Using Single-Phase Input Clock. - Ankur Bal; Rupesh Singh; Aradhana Kumari; Vikas Dhanda (IEEE Trans. Circuits Syst. II Express Briefs, 2022)