Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation. - Gang Wu 002; Ankur Sharma 001; Chris C. N. Chu (ASYNC, 2015)

Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading. - Ankur Sharma 001; David G. Chinnery; Sarvesh Bhardwaj; Chris C. N. Chu (ICCAD, 2015)

Rapid gate sizing with fewer iterations of Lagrangian Relaxation. - Ankur Sharma 001; David G. Chinnery; Shrirang Dhamdhere; Chris Chu (ICCAD, 2017)

Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach. - Ankur Sharma 001; David G. Chinnery; Chris Chu (ISPD, 2019)

Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations. - Ankur Sharma 001; David G. Chinnery; Tiago Reimann; Sarvesh Bhardwaj; Chris Chu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Integrating LR Gate Sizing in an Industrial Place-and-Route Flow. - David G. Chinnery; Ankur Sharma 001 (ISPD, 2022)