Compression-relaxation: a new approach to performance driven placement for regular architectures. - Anmol Mathur; C. L. Liu 001 (ICCAD, 1994)

Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. - Anmol Mathur; Kuang-Chien Chen; C. L. Liu 001 (FPGA, 1995)

Re-engineering of timing constrained placements for regular architectures. - Anmol Mathur; Kuang-Chien Chen; C. L. Liu 001 (ICCAD, 1995)

Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs. - Anmol Mathur; C. L. Liu 001 (ED&TC, 1996)

Generalized Kraft's Inequality and Discrete k-Modal Search. - Anmol Mathur; Edward M. Reingold (SIAM J. Comput., 1996)

An Efficient Assertion Checker for Combinational Properties. - Gagan Hasteer; Anmol Mathur; Prithviraj Banerjee (DAC, 1997)

RATAN: A tool for rate analysis and rate constraint debugging for embedded systems. - Ali Dasdan; Anmol Mathur; Rajesh K. Gupta 001 (ED&TC, 1997)

Timing-driven placement for regular architectures. - Anmol Mathur; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

An Implicit Algorithm for Finding Steady States and its Application to FSM Verification. - Gagan Hasteer; Anmol Mathur; Prithviraj Banerjee (DAC, 1998)

Efficient equivalence checking of multi-phase designs using retiming. - Gagan Hasteer; Anmol Mathur; Prithviraj Banerjee (ICCAD, 1998)

Efficient equivalence checking of multi-phase designs using phase abstraction and retiming. - Gagan Hasteer; Anmol Mathur; Prithviraj Banerjee (ACM Trans. Design Autom. Electr. Syst., 1998)

Rate analysis for embedded systems. - Anmol Mathur; Ali Dasdan; Rajesh K. Gupta 001 (ACM Trans. Design Autom. Electr. Syst., 1998)

Improved Merging of Datapath Operators using Information Content and Required Precision Analysis. - Anmol Mathur; Sanjeev Saluja (DAC, 2001)

Graph Transformations for Improved Tree Height Reduction. - G. N. Mangalam; Sanjiv Narayan; Paul van Besouw; LaNae J. Avra; Anmol Mathur; Sanjeev Saluja (VLSI Design, 2003)

Embedded tutorial: formal equivalence checking between system-level models and RTL. - Alfred Kölbl; Yuan Lu; Anmol Mathur (ICCAD, 2005)

Sequential Equivalence Checking. - Anmol Mathur; Masahiro Fujita; M. Balakrishnan; Raj S. Mitra (VLSI Design, 2006)

Design for Verification in System-level Models and RTL. - Anmol Mathur; Venkat Krishnaswamy (DAC, 2007)

Non-cycle-accurate sequential equivalence checking. - Pankaj Chauhan; Deepak Goyal; Gagan Hasteer; Anmol Mathur; Nikhil Sharma (DAC, 2009)

Power Reduction Techniques and Flows at RTL and System Level. - Anmol Mathur; Qi Wang (VLSI Design, 2009)

Functional Equivalence Verification Tools in High-Level Synthesis Flows. - Anmol Mathur; Masahiro Fujita; Edmund M. Clarke; Pascal Urard (IEEE Des. Test Comput., 2009)

Low-Power Design Using the Si2 Common Power Format. - Susan Carver; Anmol Mathur; Lalit Sharma; Prasad Subbarao; Steve Urish; Qi Wang (IEEE Des. Test Comput., 2012)

Deep-Learning Based Beam Selection Technique for 6G Millimeter Wave Communication. - Satya Kumar Vankayala; Swaraj Kumar; Thirumulanathan D; Anmol Mathur; Seungil Yoon; Issaac Kommineni (PIMRC, 2022)