VLSI Implementation of Online Digital Watermarking Technique with Difference Encoding for 8-Bit Gray Scale Images. - Annajirao Garimella; M. V. V. Satyanarayana; R. Satish Kumar; P. S. Murugesh; U. C. Niranjan (VLSI Design, 2003)

Low-Voltage Universal Cell (LVUC): A Compact Analog/Digital Logic Block for Mixed Signal FPGAs. - Lalitha Mohana Kalyani-Garimella; Annajirao Garimella; Jaime Ramírez-Angulo; Ramón González Carvajal; Antonio J. López-Martín (CICC, 2006)

Low voltage gain boosting schemes for one stage operational amplifiers. - Jaime Ramírez-Angulo; Annajirao Garimella; Lalitha Mohana Kalyani-Garimella; Milind S. Sawant; Antonio Lopez-Martin; Ramón González Carvajal (ECCTD, 2007)

An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators. - Jaime Ramírez-Angulo; Lalitha Mohana Kalyani-Garimella; Annajirao Garimella; Sri Raga Sudha Garimella; Antonio J. López-Martín; Ramón González Carvajal (VLSI Design, 2008)

A 1.21V, 100mA, 0.1µF-10µF output capacitor low drop-out voltage regulator for SoC applications. - Annajirao Garimella; Paul M. Furth (ICECS, 2009)

Single Miller compensation using inverting current buffer for multi-stage amplifiers. - Annajirao Garimella; M. Wasequr Rashid; Paul M. Furth (ISCAS, 2010)

Reverse Nested Miller Compensation Using Current Buffers in a Three-Stage LDO. - Annajirao Garimella; M. Wasequr Rashid; Paul M. Furth (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 22dB PSRR enhancement in a two-stage CMOS opamp using tail compensation. - Paul M. Furth; Sri Harsh Pakala; Annajirao Garimella; Chaitanya Mohan (CICC, 2012)

Low dropout (LDO) voltage regulator design using split-length compensation. - Paul M. Furth; Nitya R. Thota; Venkat Harish Nammi; Annajirao Garimella (MWSCAS, 2012)

Embedded Tutorial ET1: Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview. - Annajirao Garimella; Punith R. Surkanti; Paul M. Furth (VLSI Design, 2012)

Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview. - Annajirao Garimella; Punith R. Surkanti; Paul M. Furth (VLSI Design, 2012)

Voltage buffer compensation using Flipped Voltage Follower in a two-stage CMOS op-amp. - Sri Harsh Pakala; Mahender Manda; Punith R. Surkanti; Annajirao Garimella; Paul M. Furth (MWSCAS, 2015)

On the analysis of low output impedance characteristic of flipped voltage follower (FVF) and FVF LDOs. - Punith R. Surkanti; Annajirao Garimella; Mahender Manda; Paul M. Furth (MWSCAS, 2017)

Flipped Voltage Follower Based Low Dropout (LDO) Voltage Regulators: A Tutorial Overview. - Punith R. Surkanti; Annajirao Garimella; Paul M. Furth (VLSID, 2018)