Learning behavior and temporary minima of two-layer neural networks. - Anne-Johan Annema; Klaas Hoen; Hans Wallinga (Neural Networks, 1994)

Feed-forward neural networks - vector decomposition analysis, modelling and analog implementation. - Anne-Johan Annema (Kluwer, 1995)

Analog weight adaptation hardware. - Anne-Johan Annema; Hans Wallinga (Neural Process. Lett., 1995)

Low-power bandgap references featuring DTMOSTs. - Anne-Johan Annema (IEEE J. Solid State Circuits, 1999)

5.5 V tolerant I/O in a 2.5 V 0.25 μm CMOS technology. - Anne-Johan Annema; Govert Geelen; Peter C. de Jong (CICC, 2000)

5.5-V I/O in a 2.5-V 0.25-μm CMOS technology. - Anne-Johan Annema; Govert J. G. M. Geelen; Peter C. de Jong (IEEE J. Solid State Circuits, 2001)

Reducing quantization noise with recursive Sigma Delta modulators. - Daniël Schinkel; Ed van Tuijl; Anne-Johan Annema (ISCAS (1), 2004)

An audio FIR-DAC in a BCD process for high power class-D amplifiers. - T. S. Doorn; Ed van Tuijl; Daniël Schinkel; Anne-Johan Annema; Marco Berkhout; Bram Nauta (ESSCIRC, 2005)

Analog/RF circuit design techniques for nanometerscale IC technologies. - Bram Nauta; Anne-Johan Annema (ESSCIRC, 2005)

Analog circuits in ultra-deep-submicron CMOS. - Anne-Johan Annema; Bram Nauta; Ronald van Langevelde; Hans Tuinhout (IEEE J. Solid State Circuits, 2005)

A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication. - Sasa Radovanovic; Anne-Johan Annema; Bram Nauta (IEEE J. Solid State Circuits, 2005)

Bandwidth of integrated photodiodes in standard CMOS for CD/DVD applications. - Sasa Radovanovic; Anne-Johan Annema; Bram Nauta (Microelectron. Reliab., 2005)

Generalized Analytical Design Equations for Variable Slope Class-E Power Amplifiers. - Mustafa Acar; Anne-Johan Annema; Bram Nauta (ICECS, 2006)

Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance. - Mustafa Acar; Anne-Johan Annema; Bram Nauta (ISCAS, 2007)

Analytical Design Equations for Class-E Power Amplifiers. - Mustafa Acar; Anne-Johan Annema; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A general weak nonlinearity model for LNAs. - Wei Cheng; Anne-Johan Annema; Jeroen A. Croon; Dirk B. M. Klaassen; Bram Nauta (CICC, 2008)

A multi-step P-cell for LNA design automation. - Wei Cheng; Anne-Johan Annema; Bram Nauta (ISCAS, 2008)

Digital Detection of Oxide Breakdown and Life-Time Extension in Submicron CMOS Technology. - Mustafa Acar; Anne-Johan Annema; Bram Nauta (ISSCC, 2008)

A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior. - Paul Veldhorst; George Goksun; Anne-Johan Annema; Bram Nauta; Berry A. J. Buter; Maarten Vertregt (ESSCIRC, 2009)

A sub-1V bandgap voltage reference in 32nm FinFET technology. - Anne-Johan Annema; Paul Veldhorst; Gerben Doornbos; Bram Nauta (ISSCC, 2009)

Noise and Nonlinearity Modeling of Active Mixers for Fast and Accurate Estimation. - Wei Cheng; Anne-Johan Annema; Jeroen A. Croon; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Investigating Dependability of Short-Range Wireless Embedded Systems through Hardware Platform Based Design. - Benaoumeur Senouci; Anne-Johan Annema; Mark J. Bentum; Hans G. Kerkhoff (DSD, 2012)

A 0.0025mm2 bandgap voltage reference for 1.1V supply in standard 0.16μm CMOS. - Anne-Johan Annema; George Goksun (ISSCC, 2012)

A wideband IM3 cancellation technique for CMOS attenuators. - Wei Cheng; Mark S. Oude Alink; Anne-Johan Annema; Gerard Wienk; Bram Nauta (ISSCC, 2012)

RF Circuit Linearity Optimization Using a General Weak Nonlinearity Model. - Wei Cheng; Mark S. Oude Alink; Anne-Johan Annema; Jeroen A. Croon; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Wideband IM3 Cancellation Technique for CMOS Π- and T-Attenuators. - Wei Cheng; Mark S. Oude Alink; Anne-Johan Annema; Gerard Wienk; Bram Nauta (IEEE J. Solid State Circuits, 2013)

A Flicker Noise/IM3 Cancellation Technique for Active Mixer Using Negative Impedance. - Wei Cheng; Anne-Johan Annema; Gerard Wienk; Bram Nauta (IEEE J. Solid State Circuits, 2013)

A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist. - Erik Olieman; Anne-Johan Annema; Bram Nauta (VLSIC, 2014)

An Interleaved Full Nyquist High-Speed DAC Technique. - Erik Olieman; Anne-Johan Annema; Bram Nauta (IEEE J. Solid State Circuits, 2015)

On the Minimum Number of States for Switchable Matching Networks. - Ettore Lorenzo Firrao; Anne-Johan Annema; Frank E. van Vliet; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Random Telegraph Signal phenomena in avalanche mode diodes: Application to SPADs. - Vishal Agarwal; Anne-Johan Annema; Satadal Dutta; Raymond J. E. Hueting; Lis K. Nanver; Bram Nauta (ESSDERC, 2016)

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. - Harijot Singh Bindra; Joeri Lechevallier; Anne-Johan Annema; Simon M. Louwsma; Ed van Tuijl; Bram Nauta (A-SSCC, 2017)

An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC. - Harijot Singh Bindra; Anne-Johan Annema; Simon M. Louwsma; Ed J. M. van Tuijl; Bram Nauta (ESSCIRC, 2017)

A 30fJ/comparison dynamic bias comparator. - Harijot Singh Bindra; Chris E. Lokin; Anne-Johan Annema; Bram Nauta (ESSCIRC, 2017)

Hardware Implementation Overhead of Switchable Matching Networks. - Ettore Lorenzo Firrao; Anne-Johan Annema; Frank E. van Vliet; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Augmentation of Class-E PA Reliability under Load Mismatch Conditions. - Jeroen Ponte; Ali Ghahremani; Maikel Huiskamp; Anne-Johan Annema; Bram Nauta (ICECS, 2018)

A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise. - Harijot Singh Bindra; Chris E. Lokin; Daniël Schinkel; Anne-Johan Annema; Bram Nauta (IEEE J. Solid State Circuits, 2018)

Outphasing Class-E Power Amplifiers: From Theory to Back-Off Efficiency Improvement. - Ali Ghahremani; Anne-Johan Annema; Bram Nauta (IEEE J. Solid State Circuits, 2018)

A Delay Spread Cancelling Waveform Characterizer for RF Power Amplifiers. - Maikel Huiskamp; Anne-Johan Annema; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. - Harijot Singh Bindra; Anne-Johan Annema; Gerard Wienk; Bram Nauta; Simon M. Louwsma (CICC, 2019)

A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator. - Harijot Singh Bindra; Anne-Johan Annema; Simon M. Louwsma; Bram Nauta (VLSI Circuits, 2019)

A +20 dBm Highly Efficient Linear Outphasing Class-E PA Without AM/AM and AM/PM Characterization Requirements. - Ali Ghahremani; Anne-Johan Annema; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Colpitts-Based Frequency Reference Achieving a Single-Trim ± 120ppm Accuracy from -50 to 170°C. - Alexander S. Delke; Anne-Johan Annema; Mark S. Oude Alink; Yanyu Jin; Jos Verlinden; Bram Nauta (CICC, 2020)

Theory and Implementation of a Load-Mismatch Protective Class-E PA System. - Jeroen Ponte; Ali Ghahremani; Maikel Huiskamp; Anne-Johan Annema; Bram Nauta (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A Single-Trim Frequency Reference Achieving ±120 ppm Accuracy From -50 °C to 170 °C. - Alexander S. Delke; Anne-Johan Annema; Mark S. Oude Alink; Yanyu Jin; Jos Verlinden; Bram Nauta (IEEE J. Solid State Circuits, 2021)

Reconstructing Aliased Frequency Spectra by Using Multiple Sample Rates. - Maikel Huiskamp; Mark S. Oude Alink; Bram Nauta; Anne-Johan Annema; Harijot Singh Bindra (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Single-Trim Frequency Reference System With 0.7 ppm/°C From -63 °C to 165 °C Consuming 210 μW at 70 MHz. - Alexander S. Delke; Thomas J. Hoen; Anne-Johan Annema; Yanyu Jin; Jos Verlinden; Bram Nauta (IEEE J. Solid State Circuits, 2023)