Creep as a reliability problem in MEMS. - Robert Modlinski; Ann Witvrouw; Petar Ratchev; Anne Jourdain; Veerle Simons; H. A. C. Tilmans; Jaap M. J. den Toonder; Robert Puers; Ingrid De Wolf (Microelectron. Reliab., 2004)

TSV metrology and inspection challenges. - Ramakanth Alapati; Youssef Travaly; Jan Van Olmen; Ricardo Cotrin Teixeira; Jan Vaes; Marc van Cauwenbergh; Anne Jourdain; Greet Verbinnen; Gino Marcuccilli; Glenn Florence; Shay Wolfling; Christine Pelissier; et al. (3DIC, 2009)

3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). - Jan Van Olmen; Jan Coenen; Wim Dehaene; Kristin De Meyer; Cedric Huyghebaert; Anne Jourdain; Guruprasad Katti; Abdelkarim Mercha; Michal Rakowski; Michele Stucchi; Youssef Travaly; Eric Beyne; et al. (3DIC, 2009)

300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications. - Anne Jourdain; Thibault Buisson; Alain Phommahaxay; Mark Privett; Dan Wallace; Sumant Sood; Peter Bisson; Eric Beyne; Youssef Travaly; Bart Swinnen (3DIC, 2010)

3D stacking using Cu-Cu direct bonding. - Y. H. Hu; C. S. Liu; M. J. Lii; Kenneth J. Rebibis; Anne Jourdain; Antonio La Manna; Gerald Beyer; Eric Beyne; C. H. Yu (3DIC, 2011)

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding. - Alain Phommahaxay; Anne Jourdain; Greet Verbinnen; Tobias Woitke; Peter Bisson; Markus Gabriel; Walter Spiess; Alice Guerrero; Jeremy McCutcheon; Rama Puligadda; Pieter Bex; Axel Van den Eede; et al. (3DIC, 2011)

MEMS packaging and reliability: An undividable couple. - Harrie A. C. Tilmans; Jeroen De Coster; Philippe Hélin; Vladimir Cherman; Anne Jourdain; Piet De Moor; Bart Vandevelde; Nga P. Pham; Joseph Zekry; Ann Witvrouw; Ingrid De Wolf (Microelectron. Reliab., 2012)

Die to wafer 3D stacking for below 10um pitch microbumps. - Jaber Derakhshandeh; Lin Hou; Inge De Preter; Carine Gerets; Samuel Suhard; Vikas Dubey; Geraldine Jamieson; Fumihiro Inoue; Tomas Webers; Pieter Bex; Giovanni Capuz; Eric Beyne; et al. (3DIC, 2016)

Extreme wafer thinning optimization for via-last applications. - Anne Jourdain; Joeri De Vos; Fumihiro Inoue; Kenneth J. Rebibis; Andy Miller; Gerald Beyer; Eric Beyne; Edward Walsby; Jash Patel; Oliver Ansell; Janet Hopkins; Huma Ashraf; et al. (3DIC, 2016)

Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling. - Anabela Veloso; Geert Eneman; An De Keersgieter; P. Favia; Andriy Hikavyy; Rongmei Chen; Anne Jourdain; N. Horiguchi (ICICDT, 2022)

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. - Rongmei Chen; Giuliano Sisto; Michele Stucchi; Anne Jourdain; Kenichi Miyaguchi; Pieter Schuddinck; P. Woeltgens; H. Lin; Naveen Kakarla; Anabela Veloso; Dragomir Milojevic; Odysseas Zografos; et al. (VLSI Technology and Circuits, 2022)

Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. - Kateryna Serbulova; S.-H. Chen; Geert Hellings; Anabela Veloso; Anne Jourdain; Dimitri Linten; Jo De Boeck; Guido Groeseneken; Julien Ryckaert; Geert Van der Plas; Eric Beyne; Eugenio Dentoni Litta; et al. (VLSI Technology and Circuits, 2022)

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections. - A. Vandooren; N. Parihar; Jacopo Franco; Roger Loo; Hiroaki Arimura; R. Rodriguez; F. Sebaai; S. Iacovo; Kevin Vandersmissen; W. Li; G. Mannaert; D. Radisic; et al. (VLSI Technology and Circuits, 2022)

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. - Anabela Veloso; Anne Jourdain; D. Radisic; Rongmei Chen; G. Arutchelvan; B. O'Sullivan; Hiroaki Arimura; Michele Stucchi; An De Keersgieter; M. Hosseini; T. Hopf; K. D'Have; et al. (VLSI Technology and Circuits, 2022)

Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN). - Eric Beyne; Anne Jourdain; Gerald Beyer (VLSI Technology and Circuits, 2023)

Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. - Giuliano Sisto; R. Preston; Rongmei Chen; Gioele Mirabelli; Anita Farokhnejad; Yun Zhou; Ivan Ciofi; Anne Jourdain; A. Veloso; Michele Stucchi; Odysseas Zografos; Pieter Weckx; et al. (VLSI Technology and Circuits, 2023)

Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias. - P. Zhao; Liesbeth Witters; Anne Jourdain; Michele Stucchi; Nicolas Jourdan 002; J. W. Maes; H. Bana; C. Zhu; R. Chukka; F. Sebaai; Kevin Vandersmissen; N. Heylen; et al. (VLSI Technology and Circuits, 2024)