Fault Modeling for the Testing of Mixed Integrated Circuits. - Anne Meixner; Wojciech Maly (ITC, 1991)

Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique. - Anne Meixner; Jash Banik (ITC, 1997)

Elimination of Traditional Functional Testing of Interface Timings at Intel. - Mike Tripp; T. M. Mak; Anne Meixner (ITC, 2003)

Design considerations and DFT to enable testing of digital interfaces. - Mike Tripp; T. M. Mak; Anne Meixner (CICC, 2004)

Testing Gbps Interfaces without a Gigahertz Tester. - T. M. Mak; Mike Tripp; Anne Meixner (IEEE Des. Test Comput., 2004)

External Loopback Testing Experiences with High Speed Serial Interfaces. - Anne Meixner; Akira Kakizawa; Benoit Provost; Serge Bedwani (ITC, 2008)

An industrial case study of analog fault modeling. - Ender Yilmaz; Anne Meixner; Sule Ozev (VTS, 2011)

Improving IO test and system evaluation via data sharing. - Anne Meixner; Salem Abdennadher (DTIS, 2012)

An IDDQ BIST approach to characterize phase-locked loop parameters. - Samed Maltabas; Osman Kubilay Ekekon; Kemal Kulovic; Anne Meixner; Martin Margala (VTS, 2013)