Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint. - Anni Lu; Xiaochen Peng; Yandong Luo; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2020)

NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro. - Anni Lu; Xiaochen Peng; Wantong Li; Hongwu Jiang; Shimeng Yu (AICAS, 2021)

Compute-in-RRAM with Limited On-chip Resources. - Anni Lu; Xiaochen Peng; Shimeng Yu (AICAS, 2021)

A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator. - Anni Lu; Xiaochen Peng; Yandong Luo; Shanshi Huang; Shimeng Yu (DATE, 2021)

Compute-in-Memory: From Device Innovation to 3D System Integration. - Shimeng Yu; Wonbo Shim; Jae Hur; Yuan-chun Luo; Gihun Choe; Wantong Li; Anni Lu; Xiaochen Peng (ESSDERC, 2021)

Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing. - Yuan-Chun Luo; Anni Lu; Jae Hur; Shaolan Li; Shimeng Yu (IMW, 2021)

Genetic Algorithm-Based Energy-Aware CNN Quantization for Processing-In-Memory Architecture. - Beomseok Kang; Anni Lu; Yun Long; Daehyun Kim 002; Shimeng Yu; Saibal Mukhopadhyay (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark. - Anni Lu; Xiaochen Peng; Wantong Li; Hongwu Jiang; Shimeng Yu (Frontiers Artif. Intell., 2021)

DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training. - Xiaochen Peng; Shanshi Huang; Hongwu Jiang; Anni Lu; Shimeng Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference. - Anni Lu; Xiaochen Peng; Yandong Luo; Shanshi Huang; Shimeng Yu (ACM Trans. Design Autom. Electr. Syst., 2021)

Machine Learning Assisted Statistical Variation Analysis of Ferroelectric Transistors: From Experimental Metrology to Predictive Modeling. - Gihun Choe; Prasanna Venkatesan Ravindran; Anni Lu; Jae Hur; Maximilian Lederer; André Reck; Sarah Lombardo; Nashrah Afroze; Josh Kacher; Asif Islam Khan; Shimeng Yu (VLSI Technology and Circuits, 2022)

Nonvolatile Capacitive Crossbar Array for In-Memory Computing. - Jae Hur; Yuan-Chun Luo; Anni Lu; Tzu-Han Wang; Shaolan Li; Asif Islam Khan; Shimeng Yu (Adv. Intell. Syst., 2022)

Robust Processing-In-Memory With Multibit ReRAM Using Hessian-Driven Mixed-Precision Computation. - Saurabh Dash; Yandong Luo; Anni Lu; Shimeng Yu; Saibal Mukhopadhyay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing. - Yuan-Chun Luo; Anni Lu; Jae Hur; Shaolan Li; Shimeng Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

CLUE: Cross-Layer Uncertainty Estimator for Reliable Neural Perception using Processing-in-Memory Accelerators. - Minah Lee; Anni Lu; Mandovi Mukherjee; Shimeng Yu; Saibal Mukhopadhyay (IJCNN, 2023)

Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems. - Anni Lu; Jae Hur; Yuan-Chun Luo; Hai Li 008; Dmitri E. Nikonov; Ian A. Young; Yang-Kyu Choi; Shimeng Yu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators. - Yuan-Chun Luo; James Read; Anni Lu; Shimeng Yu (ASPDAC, 2024)

Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization. - Anni Lu; Junmo Lee; Yuan-Chun Luo; Hai Li 008; Ian A. Young; Shimeng Yu (DAC, 2024)

Algorithm-Hardware Co-design for Deep Learning and Probabilistic Computing with Compute-in-Memory Accelerators. - Anni Lu (2024)

A Heterogeneous Platform for 3D NAND-Based In-Memory Hyperdimensional Computing Engine for Genome Sequencing Applications. - Po-Kai Hsu; Vaidehi Garg; Anni Lu; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node. - Junmo Lee; Anni Lu; Wantong Li; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture. - Yuan-Chun Luo; Anni Lu; Yandong Luo; Sou-Chi Chang; Uygar Avci; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads. - Yuan-Chun Luo; Anni Lu; Janak Sharda; Moritz Scherer 001; Jorge Tomás Gómez; Syed Shakib Sarwar; Ziyun Li; Reid Frederick Pinkham; Barbara De Salvo; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

16 Arrays of 32 All-to-All Coupled CMOS Oscillators for AI Inference and Combinatorial Optimization. - Hai Li 008; James S. Ayers; Anni Lu; You Li 002; Dmitri E. Nikonov; Yongping Fan; Ian A. Young (CICC, 2025)

Digital Compute-in-Memory Ising Annealer with Ferroelectric Capacitor-Based nvSRAM for Combinatorial Optimization Problems. - Yuyao Kong; Jianwei Jia; Anni Lu; Faaiq G. Waqar; Yuan-Chun Luo; Hai Li 001; Ian A. Young; Shimeng Yu (ISCAS, 2025)

Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories. - Faaiq G. Waqar; Jiahao Zhang; Anni Lu; Zifan He; Jason Cong; Shimeng Yu (CoRR, 2025)

NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities. - James Read; Ming-Yen Lee; Wei-Hsing Huang; Yuan-Chun Luo; Anni Lu; Shimeng Yu (CoRR, 2025)