Test Data Compression for System-on-a-Chip Using Golomb Codes. - Anshuman Chandra; Krishnendu Chakrabarty (VTS, 2000)

Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip. - Anshuman Chandra; Krishnendu Chakrabarty (DAC, 2001)

Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding. - Anshuman Chandra; Krishnendu Chakrabarty (DATE, 2001)

Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression. - Anshuman Chandra; Krishnendu Chakrabarty (VTS, 2001)

Test Resource Partitioning for SOCs. - Anshuman Chandra; Krishnendu Chakrabarty (IEEE Des. Test Comput., 2001)

System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes. - Anshuman Chandra; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters. - Anshuman Chandra; Krishnendu Chakrabarty; Mark C. Hansen (VLSI Design, 2001)

Test Resource Partitioning for System-on-a-Chip. - Krishnendu Chakrabarty; Vikram Iyengar; Anshuman Chandra (Kluwer / Springer, 2002)

Reduction of SOC test data volume, scan power and testing time using alternating run-length codes. - Anshuman Chandra; Krishnendu Chakrabarty (DAC, 2002)

Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression. - Anshuman Chandra; Krishnendu Chakrabarty (DATE, 2002)

How Effective are Compression Codes for Reducing Test Data Volume? - Anshuman Chandra; Krishnendu Chakrabarty; Rafael A. Medina (VTS, 2002)

Low-power scan testing and test data compression forsystem-on-a-chip. - Anshuman Chandra; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Test data compression and decompression based on internal scanchains and Golomb coding. - Anshuman Chandra; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. - Yinhe Han 001; Yongjun Xu 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (Asian Test Symposium, 2003)

A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization. - Vikram Iyengar; Anshuman Chandra; Sharon Schweizer; Krishnendu Chakrabarty (DATE, 2003)

A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design. - Vikram Iyengar; Anshuman Chandra (DFT, 2003)

Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes. - Anshuman Chandra; Krishnendu Chakrabarty (IEEE Trans. Computers, 2003)

A unified approach to reduce SOC test data volume, scan power and testing time. - Anshuman Chandra; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Rapid and Energy-Efficient Testing for Embedded Cores. - Yinhe Han 001; Yu Hu 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (Asian Test Symposium, 2004)

Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. - Yinhe Han 001; Yu Hu 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (DFT, 2004)

Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes. - Anshuman Chandra; Krishnendu Chakrabarty (J. Electron. Test., 2004)

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. - Yinhe Han 001; Xiaowei Li 001; Shivakumar Swaminathan; Yu Hu 001; Anshuman Chandra (Asian Test Symposium, 2005)

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. - Yinhe Han 001; Yu Hu 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra; Xiaoqing Wen (IEICE Trans. Inf. Syst., 2005)

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. - Yinhe Han 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra (J. Comput. Sci. Technol., 2005)

Response compaction for system-on-a-chip based on advanced convolutional codes. - Yinhe Han 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (Sci. China Ser. F Inf. Sci., 2006)

Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes. - Yinhe Han 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra (IEEE Trans. Instrum. Meas., 2006)

Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction. - Anshuman Chandra; Haihua Yan; Rohit Kapur (VTS, 2007)

DFT MAX and Power. - Rohit Kapur; T. Finklea; Felix Ng; Anshuman Chandra; Sanjay Ramnath; Peter Wohl; Thomas W. Williams; Ashok Anbalan; Sandeep S. Kulkarni; Tammy Fernandes; Pramod Notiyath; Rajesh Uppuluri (J. Low Power Electron., 2007)

Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. - Yinhe Han 001; Yu Hu 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Not All Xs are Bad for Scan Compression. - Anshuman Chandra; Rohit Kapur (ATS, 2008)

Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction. - Anshuman Chandra; Felix Ng; Rohit Kapur (DATE, 2008)

Interval Based X-Masking for Scan Compression Architectures. - Anshuman Chandra; Rohit Kapur (ISQED, 2008)

Bounded Adjacent Fill for Low Capture Power Scan Testing. - Anshuman Chandra; Rohit Kapur (VTS, 2008)

Scalable Adaptive Scan (SAS). - Anshuman Chandra; Rohit Kapur; Yasunari Kanzawa (DATE, 2009)

Proactive management of X's in scan chains for compression. - Anshuman Chandra; Yasunari Kanzawa; Rohit Kapur (ISQED, 2009)

3D-Scalable Adaptive Scan (3D-SAS). - Uzair Shah Syed; Krishnendu Chakrabarty; Anshuman Chandra; Rohit Kapur (3DIC, 2011)

Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C). - Anshuman Chandra; Jyotirmoy Saikia; Rohit Kapur (Asian Test Symposium, 2011)

Special session 11B: Hot topic on-chip clocking - Industrial trends. - Anshuman Chandra (VTS, 2013)

A Case Study on Implementing Compressed DFT Architecture. - Anshuman Chandra; Subramanian Chebiyam; Rohit Kapur (ATS, 2014)

Unifying scan compression. - Swapnil Bahl; Shreyans Rungta; Shray Khullar; Rohit Kapur; Anshuman Chandra; Salvatore Talluto 001; Pramod Notiyath; Ajay Rajagopalan (DFT, 2014)

Designing effective scan compression solutions for industrial circuits. - Subramanian Chebiyam; Anshuman Chandra; Rohit Kapur (ISQED, 2015)

Designing efficient combinational compression architecture for testing industrial circuits. - Anshuman Chandra; Santosh Kulkarni 002; Subramanian Chebiyam; Rohit Kapur (VDAT, 2015)

A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation. - Anshuman Chandra; Moiz Khan; Ankita Patidar; Fumiaki Takashima; Sandeep Kumar Goel; Bharath Shankaranarayanan; Vuong Nguyen; Vistrita Tyagi; Manish Arora (ITC, 2023)

New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405. - Erik Jan Marinissen; Adrian Evans; Po-Yao Chuang; Martin Keim; Anshuman Chandra (ETS, 2024)

Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard. - Sandeep Kumar Goel; Ankita Patidar; Moiz Khan; Frank Lee 004; Anshuman Chandra; Martin Keim; Naim Lemar; Jonathan Gaudet; Quoc Phan; Vidya Neerkundar (ITC, 2024)

Testing Functional Interfaces And Complex PADs Within Multi-Die Packages With IEEE P3405. - Anshuman Chandra; Nir Sever; Martin Keim (ETS, 2025)

DFT Techniques For Efficient 3D IC Interconnect Test For Chiplet and Multi-Die Package. - Anshuman Chandra; Chi-Chun Yang; Quoc Phan; Martin Keim (ETS, 2025)

Test, Debug, and Repair for Chiplet-Based Designs. - Anshuman Chandra; Esteban Garita-Rodríguez; Pradipta Ghosh (VTS, 2025)