A 0.5V Voltage-Combiner Based Pseudo Differential OTA Design in CMOS Using Weakly Inverted Transistors. - Antaryami Panigrahi; Abhipsa Parhi (iNIS, 2016)

A 1.8 V Gain Enhanced Fully Differential Doubly-Recycled Cascode OTA with 100 dB Gain 200 MHz UGB in CMOS. - Antaryami Panigrahi; Abhipsa Parhi (VDAT, 2017)

1.2 V, 12.5 MHz fourth-order low-pass filter with 83 dB stopband attenuation using low output impedance source follower in 45 nm CMOS. - Antaryami Panigrahi; Abhipsa Parhi (IET Circuits Devices Syst., 2018)

Analysis and Modelling of pMOS based Classical Low Drop Out Regulators: A Time Domain Perspective. - Antaryami Panigrahi; Gaurav Jyoti Dutta; Swarnav Bora; Kaushik Roy Baruah; Mukul Paul (iSES, 2021)