Obtaining digital gradient signals for analog adaptive filters. - Anthony Chan Carusone; David A. Johns (ISCAS (3), 1999)

Analog filter adaptation using a dithered linear search algorithm. - Anthony Chan Carusone; David A. Johns (ISCAS (4), 2002)

A 5th order Gm-C filter in 0.25 µm CMOS with digitally programmable poles and zeroes. - Anthony Chan Carusone; David A. Johns (ISCAS (4), 2002)

A sigma-delta based open-loop frequency modulator. - Denis Daly; Anthony Chan Carusone (ISCAS (1), 2003)

Clock recovery in high-speed multilevel serial links. - Faisal A. Musa; Anthony Chan Carusone (ISCAS (5), 2003)

Digital LMS adaptation of analog filters without gradient information. - Anthony Chan Carusone; David A. Johns (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization. - Shahriar Shahramian; Tony Chan Carusone (ISCAS (3), 2004)

A 40 Gb/s transversal filter in 0.18 μm CMOS using distributed amplifiers. - Jonathan Sewter; Anthony Chan Carusone (CICC, 2005)

Jitter equalization for binary baseband communication. - Anthony Chan Carusone (ISCAS (2), 2005)

Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity. - Ahmad Darabiha; Anthony Chan Carusone; Frank R. Kschischang (ISCAS (5), 2005)

A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systems. - Jonathan Sewter; Anthony Chan Carusone (ISCAS (2), 2005)

A 19-GHz Broadband Amplifier Using a gm-Boosted Cascode in 0.18-μm CMOS. - Masum Hossain; Anthony Chan Carusone (CICC, 2006)

A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology. - Shahriar Shahramian; Sorin P. Voinigescu; Anthony Chan Carusone (CICC, 2006)

A bit-serial approximate min-sum LDPC decoder and FPGA implementation. - Ahmad Darabiha; Anthony Chan Carusone; Frank R. Kschischang (ISCAS, 2006)

A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-$muhbox m$SiGe BiCMOS Technology. - Adesh Garg; Anthony Chan Carusone; Sorin P. Voinigescu (IEEE J. Solid State Circuits, 2006)

A CMOS finite impulse response filter with a crossover traveling wave topology for equalization up to 30 Gb/s. - Jonathan Sewter; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2006)

A 3-Tap FIR Filter With Cascaded Distributed Tap Amplifiers for Equalization Up to 40 Gb/s in 0.18-$mu$m CMOS. - Jonathan Sewter; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2006)

Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology. - Shahriar Shahramian; Anthony Chan Carusone; Sorin P. Voinigescu (IEEE J. Solid State Circuits, 2006)

An Equalizer Adaptation Algorithm to Reduce Jitter in Binary Receivers. - Anthony Chan Carusone (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A Baud-Rate Timing Recovery Scheme With a Dual-Function Analog Filter. - Faisal A. Musa; Anthony Chan Carusone (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS. - Ahmad Darabiha; Anthony Chan Carusone; Frank R. Kschischang (CICC, 2007)

Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links. - Mike Bichan; Anthony Chan Carusone (ISCAS, 2007)

Modeling and Design of Multilevel Bang-Bang CDRs in the Presence of ISI and Noise. - Faisal A. Musa; Anthony Chan Carusone (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Editorial ISCAS 2006 Special Section on Analog Circuits and Systems. - Tuna B. Tarim; Anthony Chan Carusone (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing. - Mike Bichan; Anthony Chan Carusone (CICC, 2008)

A 32/16 Gb/s 4/2-PAM transmitter with PWM pre-Emphasis and 1.2 Vpp per side output swing in 0.13-μm CMOS. - Horace Cheng; Anthony Chan Carusone (CICC, 2008)

20 GHz low power QVCO and De-skew techniques in 0.13μm digital CMOS. - Masum Hossain; Anthony Chan Carusone (CICC, 2008)

High-performance chip-to-chip signaling. - Anthony Chan Carusone (ICECS, 2008)

A passive filter aided timing recovery scheme. - Faisal A. Musa; Anthony Chan Carusone (ISCAS, 2008)

Power Reduction Techniques for LDPC Decoders. - Ahmad Darabiha; Anthony Chan Carusone; Frank R. Kschischang (IEEE J. Solid State Circuits, 2008)

A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR. - Kentaro Yamamoto; Anthony Chan Carusone; Francis P. Dawson (IEEE J. Solid State Circuits, 2008)

Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity. - Ahmad Darabiha; Anthony Chan Carusone; Frank R. Kschischang (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Time-Interleaved DeltaSigma-DAC Architecture Clocked at the Nyquist Rate. - Jennifer Pham; Anthony Chan Carusone (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

An Anti-aliasing Multi-rate SigmaDelta Modulator. - Anthony Chan Carusone; Franco Maloberti (ISCAS, 2009)

Introduction to the Special Issue on the 2008 IEEE Custom Integrated Circuits Conference. - Lawrence T. Clark; Anthony Chan Carusone; Payam Heydari (IEEE J. Solid State Circuits, 2009)

CMOS Oscillators for Clock Distribution and Injection-Locked Deskew. - Masum Hossain; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2009)

A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees. - Shahriar Shahramian; Sorin P. Voinigescu; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2009)

A 32/16-Gb/s Dual-Mode Pulsewidth Modulation Pre-Emphasis (PWM-PE) Transmitter With 30-dB Loss Compensation Using a High-Speed CML Design Methodology. - Anthony Chan Carusone; Horace Cheng; Faisal A. Musa (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Guest Editorial Special Issue on ISCAS 2008. - Anthony Chan Carusone; Yehea Ismail; Un-Ku Moon; Hanspeter Schmid; Wouter A. Serdijn; Gianluca Setti (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Introducing Jump-Start Tutorials. - Anthony Chan Carusone; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Progress and trends in multi-Gbps optical receivers with CMOS integrated photodetectors. - Anthony Chan Carusone; Hemesh Yasotharan; Tony Shuo-Chun Kao (CICC, 2010)

Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver. - Dustin Dunwell; Anthony Chan Carusone (CICC, 2010)

A 15-Gb/s preamplifier with 10-dB gain control and 8-mV sensitivity in 65-nm CMOS. - Dustin Dunwell; Anthony Chan Carusone (ISCAS, 2010)

A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS. - Masum Hossain; Anthony Chan Carusone (ISSCC, 2010)

5-10 Gb/s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS. - Masum Hossain; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2010)

Multi-Gb/s Bit-by-Bit Receiver Architectures for 1-D Partial-Response Channels. - Masum Hossain; Anthony Chan Carusone (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A 5-Gbit/s CMOS Optical Receiver With Integrated Spatially Modulated Light Detector and Equalization. - Tony Shuo-Chun Kao; Faisal A. Musa; Anthony Chan Carusone (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A 1-1-1-1 MASH delta-sigma modulator using dynamic comparator-based OTAs. - Kentaro Yamamoto; Anthony Chan Carusone (CICC, 2011)

CMOS Technology Scaling Considerations for Multi-Gbps Optical Receivers With Integrated Photodetectors. - Anthony Chan Carusone; Hemesh Yasotharan; Tony Shuo-Chun Kao (IEEE J. Solid State Circuits, 2011)

7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS. - Masum Hossain; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2011)

Design of a Dual W- and D-Band PLL. - Shahriar Shahramian; Adam Hart; Alexander Tomkins; Anthony Chan Carusone; Patrice Garcia; Pascal Chevalier 002; Sorin P. Voinigescu (IEEE J. Solid State Circuits, 2011)

A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on. - Dustin Dunwell; Anthony Chan Carusone; Jared Zerbe; Brian S. Leibowitz; Barry Daly; John C. Eble (CICC, 2012)

A dead-zone free and linearized digital PLL. - Amer Samarah; Anthony Chan Carusone (ICECS, 2012)

10-40 Gb/s I/O design for data communications. - Ken Chang; Tony Chan Carusone; Ali Sheikholeslami; Bob Payne; Miki Moyal; John T. Stonick; Hisakatsu Yamaguchi (ISSCC, 2012)

A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs. - Kentaro Yamamoto; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2012)

Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters. - Shayan Shahramian; Hemesh Yasotharan; Anthony Chan Carusone (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Channel characterization using jitter measurements. - Dustin Dunwell; Atul Gupta; Anthony Chan Carusone (ISCAS, 2013)

F5: Frequency generation and clock distribution. - Antonio Liscidini; SeongHwan Cho; Tony Chan Carusone; Tanay Karnik; Mike Keaveney; Brian Otis; Aaron Partridge; Christoph Sandner (ISSCC, 2013)

A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC. - Amer Samarah; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2013)

Modeling Oscillator Injection Locking Using the Phase Domain Response. - Dustin Dunwell; Anthony Chan Carusone (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS. - Shayan Shahramian; Anthony Chan Carusone (ESSCIRC, 2014)

Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS. - Luke Wang; Qiwei Wang; Anthony Chan Carusone (ESSCIRC, 2014)

A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC. - Mike Bichan; Dustin Dunwell; Qiwei Wang; Anthony Chan Carusone (ISCAS, 2014)

A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS. - Behzad Dehlaghi; Anthony Chan Carusone (CICC, 2015)

Multi-phase bang-bang digital phase lock loop with accelerated frequency acquisition. - Amer Samarah; Anthony Chan Carusone (ISCAS, 2015)

Cycle-slipping pull-in range of bang-bang PLLs. - Amer Samarah; Anthony Chan Carusone (NEWCAS, 2015)

A 26-Gb/s 1.80-pJ/b CMOS-driven transmitter for 850-nm common-cathode VCSELs. - M. Shibata; Anthony Chan Carusone (OFC, 2015)

A 19.6-Gbps CMOS optical receiver with local feedback IIR DFE. - Alireza Sharif Bakhtiar; Anthony Chan Carusone (VLSIC, 2015)

A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS. - Shayan Shahramian; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2015)

Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS". - Shayan Shahramian; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2015)

23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs. - Shayan Shahramian; Behzad Dehlaghi; Anthony Chan Carusone (ISSCC, 2016)

A 20 Gb/s CMOS Optical Receiver With Limited-Bandwidth Front End and Local Feedback IIR-DFE. - Alireza Sharif Bakhtiar; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2016)

A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication. - Behzad Dehlaghi; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2016)

Capacitively-Coupled CMOS VCSEL Driver Circuits. - Victor Kozlov; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2016)

Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5 µs. - Shayan Shahramian; Behzad Dehlaghi; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2016)

A 40-Gbps 0.5-pJ/bit VCSEL driver in 28nm CMOS with complex zero equalizer. - Alireza Sharif Bakhtiar; Michael G. Lee; Anthony Chan Carusone (CICC, 2017)

Low-power CMOS receivers for short reach optical communication. - Alireza Sharif Bakhtiar; Michael G. Lee; Anthony Chan Carusone (CICC, 2017)

A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS. - Qiwei Wang; Hajime Shibata; Anthony Chan Carusone; Antonio Liscidini (CICC, 2017)

A sub-mW spectrum sensing architecture for portable IEEE 802.22 cognitive radio applications. - Kevin Banovic; Tony Chan Carusone (ISCAS, 2017)

Filtering ADCs for wireless receivers: A survey. - Qiwei Wang; Antonio Liscidini; Anthony Chan Carusone (MWSCAS, 2017)

A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET. - Luke Wang; Marc-Andre LaCroix; Anthony Chan Carusone (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters. - Shuai Chen; Luke Wang; Hong Zhang 009; Rosanah Murugesu; Dustin Dunwell; Anthony Chan Carusone (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Direct Time-of-Flight TCSPC Analytical Modeling Including Dead-Time Effects. - Foad Arvani; Tony Chan Carusone (ISCAS, 2018)

A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET. - Luke Wang; Yingying Fu; Marc-Andre LaCroix; Euhan Chong; Anthony Chan Carusone (ISSCC, 2018)

A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers. - Qiwei Wang; Hajime Shibata; Antonio Liscidini; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2018)

A Sub-mW Integrating Mixer SAR Spectrum Sensor for Portable Cognitive Radio Applications. - Kevin Banovic; Anthony Chan Carusone (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Nano-Watt MOS-Only Voltage Reference With High-Slope PTAT Voltage Generators. - Hong Zhang 009; Xipeng Liu; Jie Zhang 039; Hongshuai Zhang; Jijun Li; Ruizhi Zhang 002; Shuai Chen; Anthony Chan Carusone (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing. - Hong Zhang 009; Junqiang Sun; Jie Zhang 039; Ruizhi Zhang 002; Anthony Chan Carusone (IEEE Trans. Very Large Scale Integr. Syst., 2018)

TDC Sharing in SPAD-Based Direct Time-of-Flight 3D Imaging Applications. - Foad Arvani; Tony Chan Carusone; Edward S. Rogers (ISCAS, 2019)

A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS. - Shayan Shahramian; Behzad Dehlaghi; Joshua Liang; Ryan Bespalko; Dustin Dunwell; James Bailey 002; Bo Wang; Alireza Sharif Bakhtiar; Michael O'Farrell; Kerry Tang; Anthony Chan Carusone; David Cassan; et al. (ISSCC, 2019)

A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET. - Luke Wang; Yingying Fu; Marc-Andre LaCroix; Euhan Chong; Anthony Chan Carusone (IEEE J. Solid State Circuits, 2019)

All-Digital Calibration Algorithms to Correct for Static Non-Linearities in ADCs. - Paul Wenbo Chen; Nijwm Wary; Luke Wang; Qiwei Wang; Anthony Chan Carusone (ISCAS, 2020)

Discrete Multitone Signalling for Wireline Communication. - Behraz Vatankhahghadim; Nijwm Wary; Anthony Chan Carusone (ISCAS, 2020)

An Adaptive Spatial Blocker Cancellation Receiver for Multiple Antenna Systems. - Rudraneil Saha; Anthony Chan Carusone (NEWCAS, 2020)

Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC). - Tony Chan Carusone; Mingoo Seok; Hsie-Chia Chang; Meng-Fan Chang (IEEE J. Solid State Circuits, 2020)

Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation. - Ming Yang 005; Shayan Shahramian; Hossein Shakiba; Henry Wong; Peter Krotnev; Anthony Chan Carusone (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers. - Ming Yang 005; Shayan Shahramian; Henry Wong; Peter Krotnev; Anthony Chan Carusone (ISCAS, 2021)

F6: Optical and Electrical Transceivers for 400GbE and Beyond. - Tony Chan Carusone; Sudip Shekhar; Yohan Frans; Wei-Zen Chen; Thomas Toifl; Munehiko Nagatani; Franz Dielacher; William Redman-White (ISSCC, 2021)

A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s. - Behraz Vatankhahghadim; Nijwm Wary; James Bailey 002; Anthony Chan Carusone (IEEE Open J. Circuits Syst., 2021)

Peak-SNR Analysis of CMOS TDCs for SPAD-Based TCSPC 3D Imaging Applications. - Foad Arvani; Anthony Chan Carusone (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes. - Dhruv Patel 002; Alireza Sharif Bakhtiar; Anthony Chan Carusone (CICC, 2022)

Design Considerations for Time-Modulated Injection-Locked Phase Interpolators and Rotators. - Yi Fan Zhang; Joshua Liang; Tony Chan Carusone (ISCAS, 2022)

Spectrally Efficient DMT Operation With BER-Informed Dynamic Bit and Power Loading. - Behraz Vatankhahghadim; Bahaa Radi; Masum Hossain; Anthony Chan Carusone (IEEE Access, 2022)

Estimation of Broadband Time-Interleaved ADC's Impairments and Performance Using Only Single-Tone Measurements. - Hong Zhang 009; Ahmad Hassan; Paul Chen; W. Martin Snelgrove; Anthony Chan Carusone (IEEE Access, 2022)

Loop Dynamics Analysis of PAM-4 Mueller-Muller Clock and Data Recovery System. - Kunal Yadav; Ping-Hsuan Hsieh; Anthony Chan Carusone (IEEE Open J. Circuits Syst., 2022)

Optimization of Quantized Analog Signal Processing Using Genetic Algorithms and μ-Law. - Qingnan Yu; Tony Chan Carusone; Antonio Liscidini (IEEE Open J. Circuits Syst., 2022)

A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs. - Mohammed Wagih Ismail; Hajime Shibata; Zhao Li; Sharvil Patil; Tony Chan Carusone (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Reconfigurable 5-Channel Ring-Oscillator-Based TDC for Direct Time-of-Flight 3D Imaging. - Foad Arvani; Tony Chan Carusone (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Optimal Optical Receivers in Nanoscale CMOS: A Tutorial. - Bahaa Radi; Diaaeldin Abdelrahman; Odile Liboiron-Ladouceur; Glenn E. R. Cowan; Tony Chan Carusone (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Design and Optimization of Low-Dropout Voltage Regulator Using Relational Graph Neural Network and Reinforcement Learning in Open-Source SKY130 Process. - Zonghao Li; Anthony Chan Carusone (ICCAD, 2023)

Inductorless Bandpass Noise-Shaping Continuous-Time Pipelined ADC Architectures. - Mohammed Wagih Ismail; Xilin Liu; Tony Chan Carusone (ISCAS, 2023)

A 32 Gb/s, 0.42 pJ/bit Passive Hybrid Simultaneous Bidirectional Transceiver for Die-to-Die Links. - Durand Jarrett-Amor; Kunal Yadav; Danny Zhang; Bangda Yang; Sadegh Jalali; Tony Chan Carusone (ISCAS, 2023)

A 112-Gb/s - 8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes. - Dhruv Patel 002; Alireza Sharif Bakhtiar; Tony Chan Carusone (IEEE J. Solid State Circuits, 2023)

Design of a Linearized Power-Efficient Dynamic Amplifier in 22nm FDSOI. - Bangda Bender Yang; Anthony Chan Carusone (ISCAS, 2024)

A 16 Gbps, 0.126 pJ/bit, Single-Ended TIA Driver with Impedance Peaking Control for SBD D2D Links. - Durand Jarrett-Amor; Tony Chan Carusone (NewCAS, 2024)

An Open-Source AMS Circuit Optimization Framework Based on Reinforcement Learning - From Specifications to Layouts. - Zonghao Li; Anthony Chan Carusone (IEEE Access, 2024)

Co-Design of Interchiplet, Package, and System Interconnect Protocols. - Tony Chan Carusone; Dustin Dunwell; Sundeep Gupta; Letizia Giuliano; Adrien Auge; Michael Klempa; Sue Hung Fung (IEEE Micro, 2025)

A Comparison of Single-Ended, NRZ Unidirectional Signaling and Single-Ended, NRZ Simultaneous-Bidirectional Signaling for Die-to-Die Links. - Durand Jarrett-Amor; Tony Chan Carusone (IEEE Micro, 2025)

Linearity Analysis of Source-Degenerated Differential Pairs for Wireline Applications. - Kunal Yadav; Ping-Hsuan Hsieh; Anthony Chan Carusone (IEEE Open J. Circuits Syst., 2025)

An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI. - Bangda Yang; Trevor C. Caldwell; Anthony Chan Carusone (IEEE Open J. Circuits Syst., 2025)

An FPGA-Accelerated Platform for Post-FEC BER Analysis of 200 Gb/s Wireline Systems. - Richard Barrie; Ming Yang 005; Hossein Shakiba; Anthony Chan Carusone (IEEE Trans. Circuits Syst. II Express Briefs, 2025)