Genetic Algorithm Based Design Optimization Of CMOS VLSI Circuits. - Anthony M. Hill; Sung-Mo Kang (PPSN, 1994)

Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits. - Chin-Chi Teng; Anthony M. Hill; Sung-Mo Kang (ICCAD, 1995)

Design techniques for high performance, energy efficient control logic. - Uming Ko; Anthony M. Hill; Poras T. Balsara (ISLPED, 1996)

Determining accuracy bounds for simulation-based switching activity estimation. - Anthony M. Hill; Sung-Mo Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Hybrid dual-threshold design techniques for high-performance processors with low-power features. - Uming Ko; Andrew Pua; Anthony M. Hill; Pranjal Srivastava (ISLPED, 1997)

Nanometer design: what hurts next...? - Robert W. Brodersen; Anthony M. Hill; John Kibarian; Desmond Kirkpatrick; Mark A. Lavin; Mitsumasa Koyanagi (DAC, 2002)

A 600-MHz VLIW DSP. - Sanjive Agarwala; Timothy Anderson; Anthony M. Hill; M. D. Ales; Raguram Damodaran; Paul Wiley; Steven Mullinnix; J. Leach; Anthony Lell; Michael Gill; Arjun Rajagopal; Abhijeet Chachad; et al. (IEEE J. Solid State Circuits, 2002)

Architecting ASIC libraries and flows in nanometer era. - Clive Bittlestone; Anthony M. Hill; Vipul Singhal; N. V. Arvind (DAC, 2003)

A 800 MHz System-on-Chip for Wireless Infrastructure Applications. - Sanjive Agarwala; Paul Wiley; Arjun Rajagopal; Anthony M. Hill; Raguram Damodaran; Lewis Nardini; Tim Anderson; Steven Mullinnix; Jose Flores; Heping Yue; Abhijeet Chachad; John Apostol; et al. (VLSI Design, 2004)

BEOL variability and impact on RC extraction. - N. S. Nagaraj; Tom Bonifield; Abha Singh; Clive Bittlestone; Usha Narasimha; Viet Le; Anthony M. Hill (DAC, 2005)

SmartExtract: Accurate Capacitance Extraction for SOC Designs. - Usha Narasimha; Anthony M. Hill; N. S. Nagaraj (VLSI Design, 2006)

A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure. - Sanjive Agarwala; Arjun Rajagopal; Anthony M. Hill; Mayur Joshi; Steven Mullinnix; Timothy Anderson; Raguram Damodaran; Lewis Nardini; Paul Wiley; Peter Groves; John Apostol; Michael Gill; et al. (ISSCC, 2007)

A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS. - Raguram Damodaran; Timothy Anderson; Sanjive Agarwala; Rama Venkatasubramanian; Michael Gill; Dhileep Gopalakrishnan; Anthony M. Hill; Abhijeet Chachad; Dheera Balasubramanian; Naveen Bhoria; Jonathan Tran; Duc Bui; et al. (VLSI Design, 2012)

Heterogeneous Multi-processor Coherent Interconnect. - Kai Chirca; Matthew Pierson; Joe Zbiciak; David Thompson; Daniel Wu; Shankar Myilswamy; Roger Griesmer; Kedar Basavaraj; Thomas Huynh; Akshit Dayal; Junbok You; Patrick Eyres; et al. (Hot Interconnects, 2013)

Challenges and Opportunities in Automotive, Industrial, and IoT Physical Design. - Anthony M. Hill (ISPD, 2018)

2.6 A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded Applications with Integrated Safety MCU, 512b Vector VLIW DSP, Embedded Vision and Imaging Acceleration. - Rama Venkatasubramanian; Don Steiss; Greg Shurtz; Tim Anderson; Kai Chirca; Raghavendra Santhanagopal; Niraj Nandan; Anish Reghunath; Hetul Sanghvi; Daniel Wu; Abhijeet Chachad; Brian Karguth; et al. (ISSCC, 2020)