Design verification using logic tests. - Warren H. Debany Jr.; Mark Gorniak; Anthony R. Macera; Kevin A. Kwiat; Heather B. Dussault; Daniel Daskiewich (RSP, 1991)

Effective concurrent test for a parallel-input multiplier using modulo 3. - Warren H. Debany Jr.; Anthony R. Macera; Daniel Daskiewich; Mark Gorniak; Kevin A. Kwiat; Heather B. Dussault (VTS, 1992)

Empirical Bounds on Fault Coverage Loss Due to LFSR Aliasing. - Warren H. Debany Jr.; Mark Gorniak; Anthony R. Macera; Daniel Daskiewich; Kevin A. Kwiat; Heather B. Dussault (VLSI Design, 1994)