An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. - Dominique Borrione; Menouer Boubekeur; Emil Dumitrescu; Marc Renaudin; Jean-Baptiste Rigaud; Antoine Siriani (HICSS, 2003)

Validation of asynchronous circuit specifications using IF/CADP. - Dominique Borrione; Menouer Boubekeur; Laurent Mounier; Marc Renaudin; Antoine Siriani (VLSI-SOC, 2003)