Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. - Maksim Jenihhin; Jaan Raik; Anton Chepurov; Raimund Ubar (ETS, 2008)

High-Level Decision Diagrams based coverage metrics for verification and test. - Maksim Jenihhin; Jaan Raik; Anton Chepurov; Uljana Reinsalu; Raimund Ubar (LATW, 2009)

PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams. - Maksim Jenihhin; Jaan Raik; Anton Chepurov; Raimund Ubar (J. Electron. Test., 2009)

Mutation analysis with high-level decision diagrams. - Hanno Hantson; Jaan Raik; Maksim Jenihhin; Anton Chepurov; Raimund Ubar; Giuseppe Di Guglielmo; Franco Fummi (LATW, 2010)

Automated design error debug using high-level decision diagrams and mutation operators. - Jaan Raik; Urmas Repinski; Anton Chepurov; Hanno Hantson; Raimund Ubar; Maksim Jenihhin (Microprocess. Microsystems, 2013)