Probabilistic equivalence checking based on high-level decision diagrams. - Anton Karputkin; Raimund Ubar; Mati Tombak; Jaan Raik (DDECS, 2011)

Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams. - Anton Karputkin; Raimund Ubar; Mati Tombak; Jaan Raik (HLDVT, 2011)

Automated correction of design errors by edge redirection on High-Level Decision Diagrams. - Anton Karputkin; Raimund Ubar; Mati Tombak; Jaan Raik (ISQED, 2012)

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. - Taavi Viilukas; Anton Karputkin; Jaan Raik; Maksim Jenihhin; Raimund Ubar; Hideo Fujiwara (J. Electron. Test., 2012)

A synthesis-agnostic behavioral fault model for high gate-level fault coverage. - Anton Karputkin; Jaan Raik (DATE, 2016)