Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang. - Nick Brown 002; Maurice Jamieson; Anton Lydike; Emilien Bauer; Tobias Grosser (SC Workshops, 2023)

Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA. - Gabriel Rodriguez-Canal; Nick Brown 002; Maurice Jamieson; Emilien Bauer; Anton Lydike; Tobias Grosser (SC Workshops, 2023)

A shared compilation stack for distributed-memory parallelism in stencil DSLs. - George Bisbas; Anton Lydike; Emilien Bauer; Nick Brown 002; Mathieu Fehr; Lawrence Mitchell; Gabriel Rodriguez-Canal; Maurice Jamieson; Paul H. J. Kelly; Michel Steuwer; Tobias Grosser (ASPLOS (3), 2024)

Artifact of "A Multi-Level Compiler Backend for Accelerated Micro-Kernels Targetting RISC-V ISA Extensions". - Alexandre Lopoukhine; Federico Ficarelli; Christos Vasiladiotis; Anton Lydike; Josse Van Delm; Alban Dutilleul; Luca Benini; Marian Verhelst; Tobias Grosser (Zenodo, 2024)

A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions. - Alexandre Lopoukhine; Federico Ficarelli; Christos Vasiladiotis; Anton Lydike; Josse Van Delm; Alban Dutilleul; Luca Benini; Marian Verhelst; Tobias Grosser (CGO, 2025)