Calculation of LFSR Seed and Polynomial Pair for BIST Applications. - Artur Jutman; Anton Tsertov; Raimund Ubar (DDECS, 2008)

Testing beyond the SoCs in a lego style. - Anton Tsertov; Artur Jutman; Sergei Devadze (EWDTS, 2010)

Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. - Anton Tsertov; Raimund Ubar; Artur Jutman; Sergei Devadze (Asian Test Symposium, 2011)

SoC and Board Modeling for Processor-Centric Board Testing. - Anton Tsertov; Raimund Ubar; Artur Jutman; Sergei Devadze (DSD, 2011)

On in-system programming of non-volatile memories. - Anton Tsertov; Sergei Devadze; Artur Jutman; Artjom Jasnetski (MIXDES, 2013)

Laboratory framework TEAM for investigating the dependability issues of microprocessor systems. - Artjom Jasnetski; Raimund Ubar; Anton Tsertov; Helena Kruus (EWME, 2014)

Software-based self-test generation for microprocessors with high-level decision diagrams. - Raimund Ubar; Anton Tsertov; Artjom Jasnetski; Marina Brik (LATW, 2014)

New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. - Artjom Jasnetski; Jaan Raik; Anton Tsertov; Raimund Ubar (DDECS, 2015)

FPGA-controlled PCBA power-on self-test using processor's debug features. - Boyang Du; Ernesto Sánchez 001; Matteo Sonza Reorda; Julio Pérez Acle; Anton Tsertov (DDECS, 2016)

High-level modeling and testing of multiple control faults in digital systems. - Artjom Jasnetski; Stephen Adeboye Oyeniran; Anton Tsertov; Mario Schölzel; Raimund Ubar (DDECS, 2016)

A suite of IEEE 1687 benchmark networks. - Anton Tsertov; Artur Jutman; Sergei Devadze; Matteo Sonza Reorda; Erik Larsson; Farrokh Ghani Zadegan; Riccardo Cantoro; Mehrdad Montazeri; Rene Krenz-Baath (ITC, 2016)

On automatic software-based self-test program generation based on high-level decision diagrams. - Artjom Jasnetski; Raimund Ubar; Anton Tsertov (LATS, 2016)

High-level test data generation for software-based self-test in microprocessors. - Adeboye Stephen Oyeniran; Artjom Jasnetski; Anton Tsertov; Raimund Ubar (MECO, 2017)

Automated software-based self-test generation for microprocessors. - Artjom Jasnetski; Raimund Ubar; Anton Tsertov (MIXDES, 2017)

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks. - Aleksa Damljanovic; Artur Jutman; Giovanni Squillero; Anton Tsertov (ETS, 2019)

Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL. - Aleksa Damljanovic; Artur Jutman; Michele Portolan; Ernesto Sánchez 001; Giovanni Squillero; Anton Tsertov (ITC, 2019)

On-Chip Sensors Data Collection and Analysis for SoC Health Management. - Konstantin Shibin; Maksim Jenihhin; Artur Jutman; Sergei Devadze; Anton Tsertov (DFT, 2023)

Special Session: In-Field ML-Assisted Intermittent Fault Localization and Management in RISC-V SoCs. - Hardi Selg; Konstantin Shibin; Anton Tsertov; Maksim Jenihhin; Peeter Ellervee; Jaan Raik (DFT, 2024)

Keynote: Cost-Efficient Reliability for Edge-AI Chips. - Maksim Jenihhin; Mahdi Taheri; Natalia Cherezova; Mohammad Hasan Ahmadilivani; Hardi Selg; Artur Jutman; Konstantin Shibin; Anton Tsertov; Sergei Devadze; Rama Mounika Kodamanchili; Ahsan Rafiq; Jaan Raik; et al. (LATS, 2024)