A Latency-Efficient Router Architecture for CMP Systems. - Antoni Roca 001; José Flich; Federico Silla; José Duato (DSD, 2010)

VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks. - Antoni Roca 001; José Flich; Federico Silla; José Duato (HiPC, 2010)

Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. - Carles Hernández 001; Antoni Roca 001; Federico Silla; José Flich; José Duato (NOCS, 2010)

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing. - Samuel Rodrigo; José Flich; Antoni Roca 001; Simone Medardoni; Davide Bertozzi; Jesús Camacho Villanueva; Federico Silla; José Duato (NOCS, 2010)

PC-Mesh: A Dynamic Parallel Concentrated Mesh. - Jesús Camacho Villanueva; José Flich; Antoni Roca 001; José Duato (ICPP, 2011)

A Distributed Switch Architecture for On-Chip Networks. - Antoni Roca 001; Carles Hernández 001; José Flich; Federico Silla; José Duato (ICPP, 2011)

Fault-Tolerant Vertical Link Design for Effective 3D Stacking. - Carles Hernández 001; Antoni Roca 001; José Flich; Federico Silla; José Duato (IEEE Comput. Archit. Lett., 2011)

Characterizing the impact of process variation on 45 nm NoC-based CMPs. - Carles Hernández 001; Antoni Roca 001; José Flich; Federico Silla; José Duato (J. Parallel Distributed Comput., 2011)

A low-latency modular switch for CMP systems. - Antoni Roca 001; José Flich; Federico Silla; José Duato (Microprocess. Microsystems, 2011)

Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. - Samuel Rodrigo; José Flich; Antoni Roca 001; Simone Medardoni; Davide Bertozzi; Jesús Camacho Villanueva; Federico Silla; José Duato (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS. - Antoni Roca 001; José Flich; Giorgos Dimitrakopoulos (FPL, 2012)

Heterogeneous network design for effective support of invalidation-based coherency protocols. - Mario Lodde; Toni Roca 001; José Flich (INA-OCMC@HiPEAC, 2012)

Enabling High-Performance Crossbars through a Floorplan-Aware Design. - Antoni Roca 001; Carles Hernández 001; José Flich; Federico Silla; José Duato (ICPP, 2012)

On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. - Carles Hernández 001; Antoni Roca 001; Federico Silla; José Flich; José Duato (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Built-in fast gather control network for efficient support of coherence protocols. - Mario Lodde; Antoni Roca 001; José Flich (IET Comput. Digit. Tech., 2013)

Silicon-aware distributed switch architecture for on-chip networks. - Antoni Roca 001; Carles Hernández 001; José Flich; Federico Silla; José Duato (J. Syst. Archit., 2013)

A hierarchical approach for generating regular floorplans. - Javier de San Pedro; Jordi Cortadella; Antoni Roca 001 (ICCAD, 2014)

Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead. - José Cano 001; José Flich; Antoni Roca 001; José Duato; Marcello Coppola; Riccardo Locatelli (IEEE Trans. Computers, 2014)

Reactive clocks with variability-tracking jitter. - Jordi Cortadella; Luciano Lavagno; Pedro Lopez; Marc Lupon; Alberto Moreno; Antoni Roca 001; Sachin S. Sapatnekar (ICCD, 2015)

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems. - Antoni Roca 001; Carles Hernández 001; Mario Lodde; José Flich (Comput. Electr. Eng., 2015)

Ring Oscillator Clocks and Margins. - Jordi Cortadella; Marc Lupon; Alberto Moreno; Antoni Roca 001; Sachin S. Sapatnekar (ASYNC, 2016)

Improving performance guarantees in wormhole mesh NoC designs. - Milos Panic; Carles Hernández 001; Jaume Abella 001; Antoni Roca 001; Eduardo Quiñones; Francisco J. Cazorla (DATE, 2016)

DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis. - Sergi Alcaide; Carles Hernández 001; Antoni Roca 001; Jaume Abella 001 (DAC, 2017)

Voltage Noise Analysis with Ring Oscillator Clocks. - Lucas Machado; Antoni Roca Perez; Jordi Cortadella (ISVLSI, 2017)