Implementation of (Normalised) RLS Lattice on Virtex. - Felix Albu; Jiri Kadlec; Christopher I. Softley; Rudolf Matousek; Antonin Hermanek; Nick Coleman; Anthony D. Fagan (FPL, 2001)

FPGA Implementation of the Adpaptive Lattice Filter. - Antonin Hermanek; Zdenek Pohl; Jiri Kadlec (FPL, 2003)

Logarithmic Arithmetic for Real Data Types and Support for Matlab/Simulink Based Rapid-FPGA-Prototyping. - Zdenek Pohl; Jan Schier; Miroslav Lícko; Antonin Hermanek; Milan Tichý; Rudolf Matousek; Jiri Kadlec (IPDPS, 2003)

Architecture design for FPGA implementation of finite interval CMA. - Antonin Hermanek; Jan Schier; Phillip A. Regalia (EUSIPCO, 2004)

Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA. - Jan Schier; Antonin Hermanek (FPL, 2004)

Using Reconfigurable HW for High Dimensional CAF Computation. - Antonin Hermanek; Michal Kunes; Michal Kvasnicka (FPL, 2006)

Efficient FPGA Implementation of Equalizer for Finite Interval Constant Modulus Algorithm. - Premysl Sucha; Zdenek Hanzálek; Antonin Hermanek; Jan Schier (IES, 2006)

Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design - Implementation of Finite Interval Constant Modulus Algorithm. - Premysl Sucha; Zdenek Hanzálek; Antonin Hermanek; Jan Schier (J. VLSI Signal Process., 2007)

The European Logarithmic Microprocesor. - John N. Coleman; Christopher I. Softley; Jiri Kadlec; Rudolf Matousek; Milan Tichý; Zdenek Pohl; Antonin Hermanek; Nico F. Benschop (IEEE Trans. Computers, 2008)

Blind image deconvolution algorithm on NVIDIA CUDA platform. - Tomas Mazanec; Antonin Hermanek; Jan Kamenický (DDECS, 2010)

Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique. - Antonin Hermanek; Michal Kunes; Milan Tichý (FPL, 2010)

Heterogeneous Platform for Stream Based Applications on FPGAs. - Jan Kloub; Tomas Mazanec; Antonin Hermanek (FPL, 2011)