Pipelined Hogenauer CIC filters using field-programmable logic and residue number system. - Antonio García 001; Uwe Meyer-Baese; Fred J. Taylor (ICASSP, 1998)

Pipelined RNS multipliers: an application to scaling. - Antonio García 001; Antonio Lloris-Ruíz (ICECS, 1998)

RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic. - Antonio García 001; Uwe Meyer-Bäse; Antonio Lloris-Ruíz; Fred J. Taylor (ISCAS (1), 1999)

A Look-Up Scheme for Scaling in the RNS. - Antonio García 001; Antonio Lloris-Ruíz (IEEE Trans. Computers, 1999)

An efficient RNS architecture for the computation of discrete wavelet transforms on programmable devices. - Javier Ramírez 001; Antonio García 001; Pedro G. Fernández; Antonio Lloris-Ruíz (EUSIPCO, 2000)

Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform. - Javier Ramírez 001; Antonio García 001; Pedro G. Fernández; Luis Parrilla 001; Antonio Lloris-Ruíz (FPL, 2000)

A new architecture to compute the discrete cosine transform using the quadratic residue number system. - Javier Ramírez Perez de Inestrosa; Antonio García 001; Pedro G. Fernández; Luis Parrilla 001; Antonio Lloris-Ruíz (ISCAS, 2000)

Design of RNS-based distributed arithmetic DWT filterbanks. - Javier Ramírez 001; Antonio García 001; Uwe Meyer-Bäse; Fred J. Taylor; Pedro G. Fernández; Antonio Lloris-Ruíz (ICASSP, 2001)

Implementation of the one dimensional discrete cosine transform using the residue number system. - Pedro G. Fernández; Javier Ramírez 001; Antonio García 001; Luis Parrilla 001; Antonio Lloris-Ruíz (ICECS, 2001)

Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic. - Uwe Meyer-Bäse; Antonio García 001; Fred J. Taylor (J. VLSI Signal Process., 2001)

Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs. - Uwe Meyer-Bäse; Javier Ramírez 001; Antonio García 001 (FPL, 2002)

U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation. - Javier Ramírez 001; Antonio García 001 (FPL, 2002)

A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems. - Daniel González; Antonio García 001; Graham A. Jullien; Javier Ramírez 001; Luis Parrilla 001; Antonio Lloris-Ruíz (PATMOS, 2002)

Design and Implementation of RNS-Based Adaptive Filters. - Javier Ramírez 001; Uwe Meyer-Bäse; Antonio García 001; Antonio Lloris-Ruíz (FPL, 2003)

A Fast QRNS-Based Algorithm for the DCT and Its Field-Programmable Logic Implementation. - Javier Ramírez 001; Antonio García 001 (J. Circuits Syst. Comput., 2003)

Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic. - Javier Ramírez 001; Antonio García 001; Uwe Meyer-Bäse; Fred J. Taylor; Antonio Lloris-Ruíz (J. VLSI Signal Process., 2003)

Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies. - Javier Ramírez 001; Uwe Meyer-Bäse; Fred J. Taylor; Antonio García 001; Antonio Lloris-Ruíz (J. VLSI Signal Process., 2003)

Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices. - Uwe Meyer-Bäse; Suhasini Rao; Javier Ramírez 001; Antonio García 001 (FPL, 2004)

Intellectual Property Protection for RNS Circuits on FPGAs. - Luis Parrilla 001; Encarnación Castillo; Antonio García 001; Antonio Lloris-Ruíz (FPL, 2004)

Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks. - Antonio García 001; Javier Ramírez 001; Uwe Meyer-Bäse; Encarnación Castillo; Antonio Lloris-Ruíz (FPL, 2005)

Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers. - Daniel González; Luis Parrilla 001; Antonio García 001; Encarnación Castillo; Antonio Lloris-Ruíz (PATMOS, 2005)

Efficient Rns-based Design of Programmable Fir Filters Targeting Fpl Technology. - Javier Ramírez 001; Uwe Meyer-Bäse; Antonio García 001 (J. Circuits Syst. Comput., 2005)

IPP Watermarking Technique for IP Core Protection on FPL Devices. - Encarnación Castillo; Luis Parrilla 001; Antonio García 001; Antonio Lloris-Ruíz; Uwe Meyer-Bäse (FPL, 2006)

Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting. - Encarnación Castillo; Luis Parrilla 001; Antonio García 001; Uwe Meyer-Bäse; Antonio Lloris-Ruíz (FPL, 2007)

Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing. - Diego Pedro Morales; Antonio García 001; Alberto J. Palma; Antonio Martínez-Olmos; Encarnación Castillo (FPL, 2007)

IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores. - Encarnación Castillo; Uwe Meyer-Bäse; Antonio García 001; Luis Parrilla 001; Antonio Lloris-Ruíz (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration. - Diego Pedro Morales; Antonio García 001; Alberto J. Palma; Miguel Ángel Carvajal; Encarnación Castillo; Luis F. Capitán-Vallvey (FPL, 2008)

Neuromorphic Configurable Architecture for Robust Motion Estimation. - Guillermo Botella Juan; Manuel Rodríguez 002; Antonio García 001; Eduardo Ros 001 (Int. J. Reconfigurable Comput., 2008)

Improved gradient-based motion estimation on reconfigurable platforms. - Guillermo Botella Juan; Uwe Meyer-Bäse; Antonio García Ríos; Luís Parrilla Roure (ERSA, 2009)

Enhanced gradient-based motion vector coprocessor. - Guillermo Botella Juan; Antonio García Ríos; Uwe Meyer-Bäse; Manuel Rodríguez 002; María C. Molina; Luís Parrilla Roure (FPL, 2009)

Robust Bioinspired Architecture for Optical-Flow Computation. - Guillermo Botella Juan; Antonio García Ríos; M. Rodriguez-Alvarez; Eduardo Ros Vidal; Uwe Meyer-Bäse; María C. Molina (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Quantization analysis and enhancement of a VLSI gradient-based motion estimation architecture. - Guillermo Botella Juan; Uwe Meyer-Bäse; Antonio García 001; Manuel Rodríguez 002 (Digit. Signal Process., 2012)

A reconstruction method for electrical capacitance tomography based on image fusion techniques. - Antonio Martínez-Olmos; Guillermo Botella Juan; Encarnación Castillo; Diego Pedro Morales; Jesus Banqueri; Antonio García 001 (Digit. Signal Process., 2012)

Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology. - Uwe Meyer-Bäse; Guillermo Botella Juan; Soumak Mookherjee; Encarnación Castillo; Antonio García 001 (Microprocess. Microsystems, 2012)

One-step wavelet-based processing for wandering and noise removing in ECG signals. - Encarnación Castillo; Diego Pedro Morales; Antonio García 001; Luis Parrilla 001; Nuria López-Ruiz; Alberto J. Palma (IWBBIO, 2013)

Efficient wavelet-based ECG processing for single-lead FHR extraction. - Encarnación Castillo; Diego Pedro Morales; Guillermo Botella Juan; Antonio García 001; Luis Parrilla 001; Alberto J. Palma (Digit. Signal Process., 2013)

Noise Suppression in ECG Signals through Efficient One-Step Wavelet Processing Techniques. - Encarnación Castillo; Diego Pedro Morales; Antonio García 001; Fernando Martínez-Martí; Luis Parrilla 001; Alberto J. Palma (J. Appl. Math., 2013)

Improvements for the applicability of power-watermarking to embedded IP cores protection: e-coreIPP. - Luis Parrilla 001; Encarnación Castillo; Elias Todorovich; Antonio García 001; Diego Pedro Morales; Guillermo Botella (Digit. Signal Process., 2015)

Comments on "Fast architecture for decimal digit multiplication". - Encarnación Castillo; Antonio Lloris-Ruíz; Antonio García 001; Luis Parrilla 001; Diego Pedro Morales (Microprocess. Microsystems, 2016)

Classification Algorithms for Fetal QRS Extraction in Abdominal ECG Signals. - Pedro Álvarez; Francisco J. Romero; Antonio García 001; Luis Parrilla 001; Encarnación Castillo; Diego Pedro Morales (IWBBIO (1), 2017)

A new area-efficient BCD-digit multiplier. - Encarnación Castillo; Antonio Lloris-Ruíz; Diego Pedro Morales; Luis Parrilla 001; Antonio García 001; Guillermo Botella (Digit. Signal Process., 2017)

Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks. - Luís Parrilla Roure; Encarnación Castillo; Juan Antonio López Ramos; José Antonio Álvarez-Bermejo; Antonio García 001; Diego Pedro Morales (Sensors, 2018)

Efficient Elliptic Curve Cryptoprocessor for enabling TLS protocol in low-cost reconfigurable SoCs. - Luís Parrilla Roure; Ahmed Mohamed Bellemou; Antonio García 001; Encarnación Castillo (DCIS, 2019)

Wearable System for Biosignal Acquisition and Monitoring Based on Reconfigurable Technologies. - Víctor Toral; Antonio García 001; Francisco J. Romero; Diego Pedro Morales; Encarnación Castillo; Luís Parrilla Roure; Francisco M. Gómez-Campos; Antonio Morillas; Alejandro Sánchez (Sensors, 2019)

Elliptic Curve Cryptography hardware accelerator for high-performance secure servers. - Luís Parrilla Roure; José Antonio Álvarez-Bermejo; Encarnación Castillo; Juan Antonio López-Ramos; Diego Pedro Morales; Antonio García 001 (J. Supercomput., 2019)

Privacy-enabled system based on Elliptic Curve Cryptography to reduce risks of contagion in pandemics. - Luis Parrilla 001; Encarnación Castillo; Antonio García 001 (DCIS, 2020)

Cost-Effective Printed Electrodes Based on Emerging Materials Applied to Biosignal Acquisition. - Víctor Toral; Encarnación Castillo; Andreas Albretch; Francisco J. Romero; Antonio García 001; Noel Rodriguez; Paolo Lugli; Diego Pedro Morales; Almudena Rivadeneyra (IEEE Access, 2020)

Window Polarization in PCA-based Analysis of Non-Invasive Fetal ECG recordings. - Luis Oyarzún; Encarnación Castillo; Luis Parrilla 001; Antonio García 001 (DCIS, 2021)

Arithmetic and Algebraic Circuits - Antonio Lloris Ruiz; Encarnación Castillo Morales; Luís Parrilla Roure; Antonio García Ríos; María José Lloris Meseguer (Springer, 2021)

Table-Free Seed Generation for Hardware Newton-Raphson Square Root and Inverse Square Root Implementations in IoT Devices. - Luis Parrilla 001; Antonio Lloris; Encarnación Castillo; Antonio García 001 (IEEE Internet Things J., 2022)

Revisiting Multiple Ring Oscillator-Based True Random Generators to Achieve Compact Implementations on FPGAs for Cryptographic Applications. - Luis Parrilla 001; Antonio García 001; Encarnación Castillo; Juan Antonio López Ramos; Uwe Meyer-Baese (Cryptogr., 2023)

Towards efficient hardware digital twins of lithium-ion batteries. - Luís Parrilla Roure; Pablo Rodríguez-Iturriaga; Juan Antonio López-Villanueva; Salvador Rodríguez-Bolívar; Encarnación Castillo; Antonio García 001 (DCIS, 2024)

Hardware Implementations of a Deep Learning Approach to Optimal Configuration of Reconfigurable Intelligence Surfaces. - Alberto Martín-Martín; Rubén Padial-Allué; Encarnación Castillo; Luis Parrilla 001; Ignacio Parellada-Serrano; Alejandro Morán; Antonio García 001 (Sensors, 2024)