A mechanism for reducing the cost of branches in RISC architectures. - Antonio González 001; José María Llabería; Jordi Cortadella (Microprocess. Microprogramming, 1988)

Instruction fetch unit for parallel execution of branch instructions. - Antonio González 001; José M. Llabería (ICS, 1989)

The Xor embedding: An embedding of hypercubes onto rings and toruses. - Antonio González 001; Miguel Valero-García (ASAP, 1993)

A survey of branch techniques in pipelined processors. - Antonio González 001 (Microprocess. Microprogramming, 1993)

MEM: A new execution model for Prolog. - Jordi Tubella; Antonio González 001 (Microprocess. Microprogramming, 1993)

Chairmen's introduction. - Mateo Valero; Jordi Cortadella; Antonio González 001 (Microprocess. Microprogramming, 1993)

Reducing Branch Delay to Zero in Pipelined Processors. - Antonio González 001; José M. Llabería (IEEE Trans. Computers, 1993)

Combining depth-first and breadth-first search in Prolog execution. - Jordi Tubella; Antonio González 001 (GULP-PRODE (2), 1994)

A Partial Breadth-First Execution Model for Prolog. - Jordi Tubella; Antonio González 001 (ICTAI, 1994)

The Multipath Parallel Execution Model for Prolog. - Antonio González 001; Jordi Tubella (PASCO, 1994)

Parallel Numerical Algorithms. - Antonio González 001 (PDP, 1994)

Design and Evaluation of an Instruction Cache for Reducing the Cost of Branches. - Antonio González 001 (Perform. Evaluation, 1994)

A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality. - Antonio González 001; Carlos Aliagas; Mateo Valero (International Conference on Supercomputing, 1995)

Hypernode reduction modulo scheduling. - Josep Llosa; Mateo Valero; Eduard Ayguadé; Antonio González 001 (MICRO, 1995)

Load Balancing in a Network Flow Optimization Code. - Enric Fontdecaba; Antonio González 001; Jesús Labarta (PARA, 1995)

Exploiting path parallelism in logic programming. - Jordi Tubella; Antonio González 001 (PDP, 1995)

Executing Algorithms with Hypercube Topology on Torus Multicomputers. - Antonio González 001; Miguel Valero-García; Luis Díaz de Cerio (IEEE Trans. Parallel Distributed Syst., 1995)

Swing module scheduling: a lifetime-sensitive approach. - Josep Llosa; Antonio González 001; Eduard Ayguadé; Mateo Valero (IEEE PACT, 1996)

Overlapping Communication and Computation in Hypercubes. - Luis Díaz de Cerio; Miguel Valero-García; Antonio González 001 (Euro-Par, Vol. I, 1996)

The Multipath Architecture for Prolog Programs. - Jordi Tubella; Antonio González 001; E. Elias (Comput. J., 1996)

Communication Pipelining in Hypercubes. - Luis Díaz de Cerio; Antonio González 001; Miguel Valero-García (Parallel Process. Lett., 1996)

Static Locality Analysis for Cache Management. - F. Jesús Sánchez; Antonio González 001; Mateo Valero (IEEE PACT, 1997)

A Methodology for User-Oriented Scalability Analysis. - Dolors Royo; Miguel Valero-García; Antonio González 001; Carme Mari (ASAP, 1997)

Memory Address Prediction for Data Speculation. - José González 002; Antonio González 001 (Euro-Par, 1997)

PARSAR: Parallelisation of a Chirp Scaling Algorithm SAR Processor. - Antonio Martínez; Fracisco Fraile; Jordi J. Mallorquí; Leonardo Nogueira; Jordi Gabaldá; Antoni Broquetas; Antonio González 001 (Euro-Par, 1997)

Virtual registers. - Antonio González 001; Mateo Valero; José González 002; Teresa Monreal Arnal (HiPC, 1997)

Speculative Execution via Address Prediction and Data Prefetching. - José González 002; Antonio González 001 (International Conference on Supercomputing, 1997)

Eliminating Cache Conflict Misses through XOR-Based Placement Functions. - Antonio González 001; Mateo Valero; Nigel P. Topham; Joan-Manuel Parcerisa (International Conference on Supercomputing, 1997)

Cache Sensitive Modulo Scheduling. - F. Jesús Sánchez; Antonio González 001 (MICRO, 1997)

The Design and Performance of a Conflict-Avoiding Cache. - Nigel P. Topham; Antonio González 001; José González 002 (MICRO, 1997)

Fast, Accurate and Flexible Data Locality Analysis. - F. Jesús Sánchez; Antonio González 001 (IEEE PACT, 1998)

Data Speculative Multithreaded Architecture. - Pedro Marcuello; Antonio González 001 (EUROMICRO, 1998)

The Latency Hiding Effectiveness of Decoupled Access/Execute Processors. - Joan-Manuel Parcerisa; Antonio González 001 (EUROMICRO, 1998)

Divide-and-Conquer Algorithms on Two-Dimensional Meshes. - Miguel Valero-García; Antonio González 001; Luis Díaz de Cerio; Dolors Royo (Euro-Par, 1998)

Software Prefetching for Software Pipelined Loops. - F. Jesús Sánchez; Antonio González 001 (HICSS (7), 1998)

Virtual-Physical Registers. - Antonio González 001; José González 002; Mateo Valero (HPCA, 1998)

Control Speculation in Multithreaded Processors through Dynamic Loop Detection. - Jordi Tubella; Antonio González 001 (HPCA, 1998)

The Potential of Data Value Speculation to Boost ILP. - José González 002; Antonio González 001 (International Conference on Supercomputing, 1998)

Speculative Multithreaded Processors. - Pedro Marcuello; Antonio González 001; Jordi Tubella (International Conference on Supercomputing, 1998)

Jacobi Orderings for Multi-Port Hypercubes. - Dolors Royo; Antonio González 001; Miguel Valero-García (IPPS/SPDP, 1998)

A Jacobi-based algorithm for computing symmetric eigenvalues and eigenvectors in a two-dimensional mesh. - Dolors Royo; Miguel Valero-García; Antonio González 001 (PDP, 1998)

Limits of Instruction Level Parallelism with Data Value Speculation. - José González 002; Antonio González 001 (VECPAR, 1998)

Data value speculation in superscalar processors. - José González 002; Antonio González 001 (Microprocess. Microsystems, 1998)

A Method for Exploiting Communication/Computation Overlap in Hypercubes. - Luis Díaz de Cerio; Miguel Valero-García; Antonio González 001 (Parallel Comput., 1998)

Modulo Scheduling with Reduced Register Pressure. - Josep Llosa; Mateo Valero; Eduard Ayguadé; Antonio González 001 (IEEE Trans. Computers, 1998)

A Cost-Effective Clustered Architecture. - Ramon Canal; Joan-Manuel Parcerisa; Antonio González 001 (IEEE PACT, 1999)

Control-Flow Speculation through Value Prediction for Superscalar Processors. - José González 002; Antonio González 001 (IEEE PACT, 1999)

The Synergy of Multithreading and Access/Execute Decoupling. - Joan-Manuel Parcerisa; Antonio González 001 (HPCA, 1999)

Exploiting Speculative Thread-Level Parallelism on a SMT Processor. - Pedro Marcuello; Antonio González 001 (HPCN Europe, 1999)

Reducing Memory Traffic Via Redundant Store Instructions. - Carlos Molina; Antonio González 001; Jordi Tubella (HPCN Europe, 1999)

Trace-Level Reuse. - Antonio González 001; Jordi Tubella; Carlos Molina (ICPP, 1999)

Clustered speculative multithreaded processors. - Pedro Marcuello; Antonio González 001 (International Conference on Supercomputing, 1999)

Dynamic removal of redundant computations. - Carlos Molina; Antonio González 001; Jordi Tubella (International Conference on Supercomputing, 1999)

A locality sensitive multi-module cache with explicit management. - F. Jesús Sánchez; Antonio González 001 (International Conference on Supercomputing, 1999)

Value Prediction for Speculative Multithreaded Architectures. - Pedro Marcuello; Jordi Tubella; Antonio González 001 (MICRO, 1999)

Delaying Physical Register Allocation through Virtual-Physical Registers. - Teresa Monreal; Antonio González 001; Mateo Valero; José González 002; Víctor Viñals (MICRO, 1999)

Software Data Prefetching for Software Pipelined Loops. - F. Jesús Sánchez; Antonio González 001 (J. Parallel Distributed Comput., 1999)

Randomized Cache Placement for Eliminating Conflicts. - Nigel P. Topham; Antonio González 001 (IEEE Trans. Computers, 1999)

Low Communication Overhead Jacobi Algorithms for Eigenvalues Computation on Hypercubes. - Dolors Royo; Antonio González 001; Miguel Valero-García (J. Supercomput., 1999)

Complete Exchange Algorithms for Meshes and Tori Using a Systematic Approach (Research Note). - Luis Díaz de Cerio; Miguel Valero-García; Antonio González 001 (Euro-Par, 2000)

A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note). - Xavier Vera; Josep Llosa; Antonio González 001; Nerina Bermudo (Euro-Par, 2000)

Dynamic Cluster Assignment Mechanisms. - Ramon Canal; Joan-Manuel Parcerisa; Antonio González 001 (HPCA, 2000)

The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures. - F. Jesús Sánchez; Antonio González 001 (ICPP, 2000)

A low-complexity issue logic. - Ramon Canal; Antonio González 001 (ICS, 2000)

A Quantitative Assessment of Thread-Level Speculation Techniques. - Pedro Marcuello; Antonio González 001 (IPDPS, 2000)

Multiple-banked register file architectures. - José-Lorenzo Cruz; Antonio González 001; Mateo Valero; Nigel P. Topham (ISCA, 2000)

An efficient solver for Cache Miss Equations. - Nerina Bermudo; Xavier Vera; Antonio González 001; Josep Llosa (ISPASS, 2000)

Instruction Scheduling for Clustered VLIW Architectures. - F. Jesús Sánchez; Antonio González 001 (ISSS, 2000)

Very low power pipelines using significance compression. - Ramon Canal; Antonio González 001; James E. Smith 001 (MICRO, 2000)

Reducing wire delay penalty through value prediction. - Joan-Manuel Parcerisa; Antonio González 001 (MICRO, 2000)

Modulo scheduling for a fully-distributed clustered VLIW architecture. - F. Jesús Sánchez; Antonio González 001 (MICRO, 2000)

Dynamic Register Renaming Through Virtual-Physical Registers. - Teresa Monreal; Antonio González 001; Mateo Valero; José González 002; Víctor Viñals (J. Instr. Level Parallelism, 2000)

Analyzing Data Locality in Numeric Applications. - F. Jesús Sánchez; Antonio González 001 (IEEE Micro, 2000)

Optimizing cache miss equations polyhedra. - Nerina Bermudo; Xavier Vera; Antonio González 001; Josep Llosa (SIGARCH Comput. Archit. News, 2000)

A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors. - Josep M. Codina; F. Jesús Sánchez; Antonio González 001 (IEEE PACT, 2001)

Confidence Estimation for Branch Prediction Reversal. - Juan L. Aragón; José González 002; José M. García 001; Antonio González 001 (HiPC, 2001)

Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow. - Juan L. Aragón; José González 002; José M. García 001; Antonio González 001 (ICCD, 2001)

Reducing the complexity of the issue logic. - Ramon Canal; Antonio González 001 (ICS, 2001)

Energy-effective issue logic. - Daniele Folegnani; Antonio González 001 (ISCA, 2001)

Graph-partitioning based instruction scheduling for clustered processors. - Alex Aletà; Josep M. Codina; F. Jesús Sánchez; Antonio González 001 (MICRO, 2001)

CALMANT: Un Método Sistemático para la Ejecución de Algoritmos Hipercubo en Sistemas Multiprocesador. - Luis Díaz de Cerio; Miguel Valero-García; Antonio González 001; Dolors Royo (Computación y Sistemas, 2001)

CALMANT: A Systematic Method for the Execution of Hypercube Algorithms in Multiprocessor Systems. - Luis Díaz de Cerio; Miguel Valero-García; Antonio González 001; Dolors Royo (Computación y Sistemas, 2001)

Dynamic Code Partitioning for Clustered Architectures. - Ramon Canal; Joan-Manuel Parcerisa; Antonio González 001 (Int. J. Parallel Program., 2001)

Clustered Modulo Scheduling in a VLIW Architecture with Distributed Cache . - F. Jesús Sánchez; Antonio González 001 (J. Instr. Level Parallelism, 2001)

Implementing the one-sided Jacobi method on a 2D/3D mesh multicomputer. - Dolors Royo; Miguel Valero-García; Antonio González 001 (Parallel Comput., 2001)

Control-Flow Speculation through Value Prediction. - José González 002; Antonio González 001 (IEEE Trans. Computers, 2001)

Lifetime-Sensitive Modulo Scheduling in a Production Environment. - Josep Llosa; Eduard Ayguadé; Antonio González 001; Mateo Valero; Jason Eckhardt (IEEE Trans. Computers, 2001)

Improving Latency Tolerance of Multithreading through Decoupling. - Joan-Manuel Parcerisa; Antonio González 001 (IEEE Trans. Computers, 2001)

Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning. - Alex Aletà; Josep M. Codina; F. Jesús Sánchez; Antonio González 001; David R. Kaeli (IEEE PACT, 2002)

Efficient Interconnects for Clustered Microarchitectures. - Joan-Manuel Parcerisa; Julio Sahuquillo; Antonio González 001; José Duato (IEEE PACT, 2002)

Thread-Spawning Schemes for Speculative Multithreading. - Pedro Marcuello; Antonio González 001 (HPCA, 2002)

Trace-Level Speculative Multithreaded Architecture. - Carlos Molina; Antonio González 001; Jordi Tubella (ICCD, 2002)

Hardware Schemes for Early Register Release. - Teresa Monreal; Víctor Viñals; Antonio González 001; Mateo Valero (ICPP, 2002)

Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms. - Jaume Abella 001; Antonio González 001; Josep Llosa; Xavier Vera (ICPP Workshops, 2002)

Dual path instruction processing. - Juan L. Aragón; José González 002; Antonio González 001; James E. Smith 001 (ICS, 2002)

A comparative study of modulo scheduling techniques. - Josep M. Codina; Josep Llosa; Antonio González 001 (ICS, 2002)

An interleaved cache clustered VLIW processor. - Enric Gibert; F. Jesús Sánchez; Antonio González 001 (ICS, 2002)

Speculative Dynamic Vectorization. - Alex Pajuelo; Antonio González 001; Mateo Valero (ISCA, 2002)

Near-Optimal Padding for Removing Conflict Misses. - Xavier Vera; Josep Llosa; Antonio González 001 (LCPC, 2002)

Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor. - Enric Gibert; F. Jesús Sánchez; Antonio González 001 (MICRO, 2002)

Errata on "Measuring Experimental Error in Microprocessor Simulation". - Rajagopalan Desikan; Doug Burger; Stephen W. Keckler; José-Lorenzo Cruz; Fernando Latorre; Antonio González 001; Mateo Valero (SIGARCH Comput. Archit. News, 2002)

Hypercube Algorithms on Mesh Connected Multicomputers. - Luis Díaz de Cerio; Miguel Valero-García; Antonio González 001 (IEEE Trans. Parallel Distributed Syst., 2002)

Optimizing Program Locality Through CMEs and GAs. - Xavier Vera; Jaume Abella 001; Antonio González 001; Josep Llosa (IEEE PACT, 2003)

Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache. - Enric Gibert; F. Jesús Sánchez; Antonio González 001 (CGO, 2003)

Value Compression to Reduce Power in Data Caches. - Carles Aliagas; Carlos Molina; Montse Garcia 002; Antonio González 001; Jordi Tubella (Euro-Par, 2003)

Power-Aware Adaptive Issue Queue and Register File. - Jaume Abella 001; Antonio González 001 (HiPC, 2003)

Power-Aware Control Speculation through Selective Throttling. - Juan L. Aragón; José González 002; Antonio González 001 (HPCA, 2003)

Power Efficient Data Cache Designs. - Jaume Abella 001; Antonio González 001 (ICCD, 2003)

On Reducing Register Pressure and Energy in Multiple-Banked Register Files. - Jaume Abella 001; Antonio González 001 (ICCD, 2003)

Dynamic Cluster Resizing. - José González 002; Antonio González 001 (ICCD, 2003)

Non redundant data cache. - Carlos Molina; Carles Aliagas; Montse Garcia 002; Antonio González 001; Jordi Tubella (ISLPED, 2003)

Instruction Replication for Clustered Microarchitectures. - Alex Aletà; Josep M. Codina; Antonio González 001; David R. Kaeli (MICRO, 2003)

Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors. - Enric Gibert; F. Jesús Sánchez; Antonio González 001 (MICRO, 2003)

A framework for modeling and optimization of prescient instruction prefetch. - Tor M. Aamodt; Pedro Marcuello; Paul Chow; Antonio González 001; Per Hammarlund; Hong Wang 003; John Paul Shen (SIGMETRICS, 2003)

Power- and Complexity-Aware Issue Queue Designs. - Jaume Abella 001; Ramon Canal; Antonio González 001 (IEEE Micro, 2003)

Software-Controlled Operand-Gating. - Ramon Canal; Antonio González 001; James E. Smith 001 (CGO, 2004)

Low-Complexity Distributed Issue Queue. - Jaume Abella 001; Antonio González 001 (HPCA, 2004)

Thermal-Aware Clustered Microarchitectures. - Pedro Chaparro; José González 002; Antonio González 001 (ICCD, 2004)

Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2. - Grigorios Magklis; José González 002; Antonio González 001 (ICCD, 2004)

Back-end assignment schemes for clustered multithreaded processors. - Fernando Latorre; José González 002; Antonio González 001 (ICS, 2004)

Cache organizations for clustered microarchitectures. - José González 002; Fernando Latorre; Antonio González 001 (WMPI, 2004)

Removing communications in clustered microarchitectures through instruction replication. - Alex Aletà; Josep M. Codina; Antonio González 001; David R. Kaeli (ACM Trans. Archit. Code Optim., 2004)

Thread Partitioning and Value Prediction for Exploiting Speculative Thread-Level Parallelism. - Pedro Marcuello; Antonio González 001; Jordi Tubella (IEEE Trans. Computers, 2004)

Late Allocation and Early Release of Physical Registers. - Teresa Monreal; Víctor Viñals; José González 002; Antonio González 001; Mateo Valero (IEEE Trans. Computers, 2004)

A fast and accurate framework to analyze and optimize cache memory behavior. - Xavier Vera; Nerina Bermudo; Josep Llosa; Antonio González 001 (ACM Trans. Program. Lang. Syst., 2004)

Compiler analysis for trace-level speculative multithreaded architectures. - Carlos Molina; Antonio González 001; Jordi Tubella (Interaction between Compilers and Computer Architectures, 2005)

Variable-Based Multi-module Data Caches for Clustered VLIW Processors. - Enric Gibert; Jaume Abella 001; F. Jesús Sánchez; Xavier Vera; Antonio González 001 (IEEE PACT, 2005)

Compiler Directed Early Register Release. - Timothy M. Jones 001; Michael F. P. O'Boyle; Jaume Abella 001; Antonio González 001; Oguz Ergin (IEEE PACT, 2005)

Value Compression for Efficient Computation. - Ramon Canal; Antonio González 001; James E. Smith 001 (Euro-Par, 2005)

Distributing the Frontend for Temperature Reduction. - Pedro Chaparro; Grigorios Magklis; José González 002; Antonio González 001 (HPCA, 2005)

Software Directed Issue Queue Power Reduction. - Timothy M. Jones 001; Michael F. P. O'Boyle; Jaume Abella 001; Antonio González 001 (HPCA, 2005)

Memory Bank Predictors. - Stefan Bieschewski; Joan-Manuel Parcerisa; Antonio González 001 (ICCD, 2005)

Inherently Workload-Balanced Clustered Microarchitecture. - Jaume Abella 001; Antonio González 001 (IPDPS, 2005)

Control-Flow Independence Reuse via Dynamic Vectorization. - Alex Pajuelo; Antonio González 001; Mateo Valero (IPDPS, 2005)

Reducing Misspeculation Penalty in Trace-Level Speculative Multithreaded Architectures. - Carlos Molina; Jordi Tubella; Antonio González 001 (ISHPC, 2005)

The Mitosis Speculative Multithreaded Architectures. - Carlos Madriles; Carlos García Quiñones; F. Jesús Sánchez; Pedro Marcuello; Antonio González 001 (PARCO, 2005)

Demystifying on-the-fly spill code. - Alex Aletà; Josep M. Codina; Antonio González 001; David R. Kaeli (PLDI, 2005)

Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices. - Carlos García Quiñones; Carlos Madriles; F. Jesús Sánchez; Pedro Marcuello; Antonio González 001; Dean M. Tullsen (PLDI, 2005)

Hardware support for early register release. - Teresa Monreal; Víctor Viñals; Antonio González 001; Mateo Valero (Int. J. High Perform. Comput. Netw., 2005)

Speculative execution for hiding memory latency. - Alex Pajuelo; Antonio González 001; Mateo Valero (SIGARCH Comput. Archit. News, 2005)

IATAC: a smart predictor to turn-off L2 cache lines. - Jaume Abella 001; Antonio González 001; Xavier Vera; Michael F. P. O'Boyle (ACM Trans. Archit. Code Optim., 2005)

Distributed Data Cache Designs for Clustered VLIW Processors. - Enric Gibert; F. Jesús Sánchez; Antonio González 001 (IEEE Trans. Computers, 2005)

An accurate cost model for guiding data locality transformations. - Xavier Vera; Jaume Abella 001; Josep Llosa; Antonio González 001 (ACM Trans. Program. Lang. Syst., 2005)

On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures. - Joan-Manuel Parcerisa; Julio Sahuquillo; Antonio González 001; José Duato (IEEE Trans. Parallel Distributed Syst., 2005)

Heterogeneous way-size cache. - Jaume Abella 001; Antonio González 001 (ICS, 2006)

Design space exploration for multicore architectures: a power/performance/thermal view. - Matteo Monchiero; Ramon Canal; Antonio González 001 (ICS, 2006)

Selective predicate prediction for out-of-order processors. - Eduardo Quiñones; Joan-Manuel Parcerisa; Antonio González 001 (ICS, 2006)

SAMIE-LSQ: set-associative multiple-instruction entry load/store queue. - Jaume Abella 001; Antonio González 001 (IPDPS, 2006)

Empowering a helper cluster through data-width aware instruction selection policies. - Osman S. Unsal; Oguz Ergin; Xavier Vera; Antonio González 001 (IPDPS, 2006)

Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture. - Grigorios Magklis; Pedro Chaparro; José González 002; Antonio González 001 (ISLPED, 2006)

Exploiting Narrow Values for Soft Error Tolerance. - Oguz Ergin; Osman S. Unsal; Xavier Vera; Antonio González 001 (IEEE Comput. Archit. Lett., 2006)

Instruction scheduling for a clustered VLIW processor with a word-interleaved cache. - Enric Gibert; F. Jesús Sánchez; Antonio González 001 (Concurr. Comput. Pract. Exp., 2006)

A dynamically reconfigurable cache for multithreaded processors. - Alex Settle; Dan Connors; Enric Gibert; Antonio González 001 (J. Embed. Comput., 2006)

Impact of Parameter Variations on Circuits and Microarchitecture. - Osman S. Unsal; James W. Tschanz; Keith A. Bowman; Vivek De; Xavier Vera; Antonio González 001; Oguz Ergin (IEEE Micro, 2006)

Control Speculation for Energy-Efficient Next-Generation Superscalar Processors. - Juan L. Aragón; José M. González; Antonio González 001 (IEEE Trans. Computers, 2006)

Early Register Release for Out-of-Order Processors with RegisterWindows. - Eduardo Quiñones; Joan-Manuel Parcerisa; Antonio González 001 (PACT, 2007)

Heterogeneous Clustered VLIW Microarchitectures. - Alex Aletà; Josep M. Codina; Antonio González 001; David R. Kaeli (CGO, 2007)

Virtual Cluster Scheduling Through the Scheduling Graph. - Josep M. Codina; F. Jesús Sánchez; Antonio González 001 (CGO, 2007)

Improving Branch Prediction and Predicated Execution in Out-of-Order Processors. - Eduardo Quiñones; Joan-Manuel Parcerisa; Antonio González 001 (HPCA, 2007)

Fuse: A Technique to Anticipate Failures due to Degradation in ALUs. - Jaume Abella 001; Xavier Vera; Osman S. Unsal; Oguz Ergin; Antonio González 001 (IOLTS, 2007)

Building a large instruction window through ROB compression. - Fernando Latorre; Grigorios Magklis; José González 002; Pedro Chaparro; Antonio González 001 (MEDEA@PACT, 2007)

Penelope: The NBTI-Aware Processor. - Jaume Abella 001; Xavier Vera; Antonio González 001 (MICRO, 2007)

Reliability: Fallacy or Reality? - Antonio González 001; Scott A. Mahlke; Shubu Mukherjee; Resit Sendag; Derek Chiou; Joshua J. Yi (IEEE Micro, 2007)

Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences. - Ronny Ronen; Antonio González 001 (IEEE Micro, 2007)

Understanding the Thermal Implications of Multi-Core Architectures. - Pedro Chaparro; José González 002; Grigorios Magklis; Qiong Cai; Antonio González 001 (IEEE Trans. Parallel Distributed Syst., 2007)

Meeting points: using thread criticality to adapt multicore hardware to parallel regions. - Qiong Cai; José González 002; Ryan N. Rakvic; Grigorios Magklis; Pedro Chaparro; Antonio González 001 (PACT, 2008)

On-Line Failure Detection and Confinement in Caches. - Jaume Abella 001; Pedro Chaparro; Xavier Vera; Javier Carretero; Antonio González 001 (IOLTS, 2008)

A software-hardware hybrid steering mechanism for clustered microarchitectures. - Qiong Cai; Josep M. Codina; José González 002; Antonio González 001 (IPDPS, 2008)

Efficient resources assignment schemes for clustered multithreaded processors. - Fernando Latorre; José González 002; Antonio González 001 (IPDPS, 2008)

Thread fusion. - José González 002; Qiong Cai; Pedro Chaparro; Grigorios Magklis; Ryan N. Rakvic; Antonio González 001 (ISLPED, 2008)

Version management alternatives for hardware transactional memory. - Marc Lupon; Grigorios Magklis; Antonio González 001 (MEDEA@PACT, 2008)

Refueling: Preventing Wire Degradation due to Electromigration. - Jaume Abella 001; Xavier Vera; Osman S. Unsal; Oguz Ergin; Antonio González 001; James W. Tschanz (IEEE Micro, 2008)

Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices. - Carlos Madriles; Carlos García Quiñones; F. Jesús Sánchez; Pedro Marcuello; Antonio González 001; Dean M. Tullsen; Hong Wang 003; John Paul Shen (IEEE Trans. Parallel Distributed Syst., 2008)

Power/Performance/Thermal Design-Space Exploration for Multicore Architectures. - Matteo Monchiero; Ramon Canal; Antonio González 001 (IEEE Trans. Parallel Distributed Syst., 2008)

FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery. - Marc Lupon; Grigorios Magklis; Antonio González 001 (PACT, 2009)

Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading. - Carlos Madriles; Pedro López 001; Josep M. Codina; Enric Gibert; Fernando Latorre; Alejandro Martínez; Raúl Martínez; Antonio González 001 (PACT, 2009)

Key Microarchitectural Innovations for Future Microprocessors. - Antonio González 001 (ARCS, 2009)

Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs. - Javier Lira; Carlos Molina; Antonio González 001 (Euro-Par, 2009)

P-slice based efficient speculative multithreading. - Rakesh Ranjan; Pedro Marcuello; Fernando Latorre; Antonio González 001 (HiPC, 2009)

LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors. - Javier Lira; Carlos Molina; Antonio González 001 (ICCD, 2009)

Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs. - Matteo Monchiero; Ramon Canal; Antonio González 001 (ICPP, 2009)

Online error detection and correction of erratic bits in register files. - Xavier Vera; Jaume Abella 001; Javier Carretero; Pedro Chaparro; Antonio González 001 (IOLTS, 2009)

End-to-end register data-flow continuous self-test. - Javier Carretero; Pedro Chaparro; Xavier Vera; Jaume Abella 001; Antonio González 001 (ISCA, 2009)

Boosting single-thread performance in multi-core systems through fine-grain multi-threading. - Carlos Madriles; Pedro López 001; Josep M. Codina; Enric Gibert; Fernando Latorre; Alejandro Martínez; Raúl Martínez; Antonio González 001 (ISCA, 2009)

Low Vccmin fault-tolerant cache with highly predictable performance. - Jaume Abella 001; Javier Carretero; Pedro Chaparro; Xavier Vera; Antonio González 001 (MICRO, 2009)

Exploring the limits of early register release: Exploiting compiler analysis. - Timothy M. Jones 001; Michael F. P. O'Boyle; Jaume Abella 001; Antonio González 001; Oguz Ergin (ACM Trans. Archit. Code Optim., 2009)

Energy-efficient register caching with compiler assistance. - Timothy M. Jones 001; Michael F. P. O'Boyle; Jaume Abella 001; Antonio González 001; Oguz Ergin (ACM Trans. Archit. Code Optim., 2009)

AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures. - Alex Aletà; Josep M. Codina; F. Jesús Sánchez; Antonio González 001; David R. Kaeli (IEEE Trans. Computers, 2009)

Reducing Soft Errors through Operand Width Aware Policies. - Oguz Ergin; Osman S. Unsal; Xavier Vera; Antonio González 001 (IEEE Trans. Dependable Secur. Comput., 2009)

Selective replication: A lightweight technique for soft errors. - Xavier Vera; Jaume Abella 001; Javier Carretero; Antonio González 001 (ACM Trans. Comput. Syst., 2009)

Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability. - Shrikanth Ganapathy; Ramon Canal; Antonio González 001; Antonio Rubio 001 (DATE, 2010)

High-Performance low-vcc in-order core. - Jaume Abella 001; Pedro Chaparro; Xavier Vera; Javier Carretero; Antonio González 001 (HPCA, 2010)

The auction: optimizing banks usage in Non-Uniform Cache Architectures. - Javier Lira; Carlos Molina; Antonio González 001 (ICS, 2010)

MODEST: a model for energy estimation under spatio-temporal variability. - Shrikanth Ganapathy; Ramon Canal; Antonio González 001; Antonio Rubio 001 (ISLPED, 2010)

MT-SBST: Self-test optimization in multithreaded multicore architectures. - Nikos Foutris; Mihalis Psarakis; Dimitris Gizopoulos; Andreas Apostolakis; Xavier Vera; Antonio González 001 (ITC, 2010)

A Dynamically Adaptable Hardware Transactional Memory. - Marc Lupon; Grigorios Magklis; Antonio González 001 (MICRO, 2010)

VCTA: A Via-Configurable Transistor Array regular fabric. - Marc Pons 001; Francesc Moll; Antonio Rubio 001; Jaume Abella 001; Xavier Vera; Antonio González 001 (VLSI-SoC, 2010)

Energy efficiency via thread fusion and value reuse. - Ryan N. Rakvic; José González 002; Qiong Cai; Pedro Chaparro; Grigorios Magklis; Antonio González 001 (IET Comput. Digit. Tech., 2010)

Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors. - Ryan N. Rakvic; Qiong Cai; José González 002; Grigorios Magklis; Pedro Chaparro; Antonio González 001 (ACM Trans. Archit. Code Optim., 2010)

Leveraging Register Windows to Reduce Physical Registers to the Bare Minimum. - Eduardo Quiñones; Joan-Manuel Parcerisa; Antonio González 001 (IEEE Trans. Computers, 2010)

Processor Microarchitecture: An Implementation Perspective - Antonio González 001; Fernando Latorre; Grigorios Magklis (Processor Microarchitecture, 2010)

A Co-designed HW/SW Approach to General Purpose Program Acceleration Using a Programmable Functional Unit. - Abhishek Deb; Josep M. Codina; Antonio González 001 (Interaction between Compilers and Computer Architectures, 2011)

Beforehand Migration on D-NUCA Caches. - Javier Lira; Timothy M. Jones 001; Carlos Molina; Antonio González 001 (PACT, 2011)

SoftHV: a HW/SW co-designed processor with horizontal and vertical fusion. - Abhishek Deb; Josep M. Codina; Antonio González 001 (Conf. Computing Frontiers, 2011)

Implementing a hybrid SRAM / eDRAM NUCA architecture. - Javier Lira; Carlos Molina; David M. Brooks; Antonio González 001 (HiPC, 2011)

Moore's law implications on energy reduction. - Antonio González 001 (HiPEAC, 2011)

Hardware/software-based diagnosis of load-store queues using expandable activity logs. - Javier Carretero; Xavier Vera; Jaume Abella 001; Tanausú Ramírez; Matteo Monchiero; Antonio González 001 (HPCA, 2011)

Fg-STP: Fine-Grain Single Thread Partitioning on Multicores. - Rakesh Ranjan; Fernando Latorre; Pedro Marcuello; Antonio González 001 (HPCA, 2011)

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors. - Shrikanth Ganapathy; Ramon Canal; Antonio González 001; Antonio Rubio 001 (ICCD, 2011)

New reliability mechanisms in memory design for sub-22nm technologies. - Nivard Aymerich; A. Asenov; Andrew R. Brown; Ramon Canal; Binjie Cheng; Joan Figueras; Antonio González 001; Enric Herrero; S. Markov; Miguel Miranda; Peyman Pouyan; Tanausú Ramírez; et al. (IOLTS, 2011)

HK-NUCA: Boosting Data Searches in Dynamic Non-Uniform Cache Architectures for Chip Multiprocessors. - Javier Lira; Carlos Molina; Antonio González 001 (IPDPS, 2011)

A Performance and Area Efficient Architecture for Intrusion Detection Systems. - Govind Sreekar Shenoy; Jordi Tubella; Antonio González 001 (IPDPS, 2011)

Thread shuffling: combining DVFS and thread migration toreduce energy consumptions for multi-core systems. - Qiong Cai; José González 002; Grigorios Magklis; Pedro Chaparro; Antonio González 001 (ISLPED, 2011)

Global productiveness propagation: a code optimization technique to speculatively prune useless narrow computations. - Indu Bhagat; Enric Gibert; F. Jesús Sánchez; Antonio González 001 (LCTES, 2011)

Accelerating microprocessor silicon validation by exposing ISA diversity. - Nikos Foutris; Dimitris Gizopoulos; Mihalis Psarakis; Xavier Vera; Antonio González 001 (MICRO, 2011)

A Power-Efficient Co-designed Out-of-Order Processor. - Abhishek Deb; Josep M. Codina; Antonio González 001 (SBAC-PAD, 2011)

Design of complex circuits using the Via-Configurable transistor array regular layout fabric. - Marc Pons 001; Francesc Moll; Antonio Rubio 001; Jaume Abella 001; Xavier Vera; Antonio González 001 (SoCC, 2011)

TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies. - Ramon Canal; Antonio Rubio 001; A. Asenov; A. Brown; Miguel Miranda; Paul Zuber; Antonio González 001; Xavier Vera (FET, 2011)

Implementing End-to-End Register Data-Flow Continuous Self-Test. - Javier Carretero; Pedro Chaparro; Xavier Vera; Jaume Abella 001; Antonio González 001 (IEEE Trans. Computers, 2011)

Compiler Directed Issue Queue Energy Reduction. - Timothy M. Jones 001; Michael F. P. O'Boyle; Jaume Abella 001; Antonio González 001 (Trans. High Perform. Embed. Archit. Compil., 2011)

CROB: Implementing a Large Instruction Window through Compression. - Fernando Latorre; Grigorios Magklis; José González 002; Pedro Chaparro; Antonio González 001 (Trans. High Perform. Embed. Archit. Compil., 2011)

Speculative dynamic vectorization for HW/SW co-designed processors. - Rakesh Kumar 003; Alejandro Martínez; Antonio González 001 (PACT, 2012)

A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance. - Shrikanth Ganapathy; Ramon Canal; Dan Alexandrescu; Enrico Costenaro; Antonio González 001; Antonio Rubio 001 (ICCD, 2012)

Hardware/Software Mechanisms for Protecting an IDS against Algorithmic Complexity Attacks. - Govind Sreekar Shenoy; Jordi Tubella; Antonio González 001 (IPDPS Workshops, 2012)

Setting an error detection infrastructure with low cost acoustic wave detectors. - Gaurang Upasani; Xavier Vera; Antonio González 001 (ISCA, 2012)

Exploiting temporal locality in network traffic using commodity multi-cores. - Govind Sreekar Shenoy; Jordi Tubella; Antonio González 001 (ISPASS, 2012)

Improving the Performance Efficiency of an IDS by Exploiting Temporal Locality in Network Traffic. - Govind Sreekar Shenoy; Jordi Tubella; Antonio González 001 (MASCOTS, 2012)

Improving the Resilience of an IDS against Performance Throttling Attacks. - Govind Sreekar Shenoy; Jordi Tubella; Antonio González 001 (SecureComm, 2012)

DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support. - Demos Pavlou; Enric Gibert; Fernando Latorre; Antonio González 001 (VEE, 2012)

A HW/SW Co-designed Programmable Functional Unit. - Abhishek Deb; Josep M. Codina; Antonio González 001 (IEEE Comput. Archit. Lett., 2012)

Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells. - Nivard Aymerich; Shrikanth Ganapathy; Antonio Rubio 001; Ramon Canal; Antonio González 001 (Integr., 2012)

The migration prefetcher: Anticipating data promotion in dynamic NUCA caches. - Javier Lira; Timothy M. Jones 001; Carlos Molina; Antonio González 001 (ACM Trans. Archit. Code Optim., 2012)

Performance analysis and predictability of the software layer in dynamic binary translators/optimizers. - Aleksandar Brankovic; Kyriakos Stavrou; Enric Gibert; Antonio González 001 (Conf. Computing Frontiers, 2013)

Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment. - Rakesh Kumar 003; Alejandro Martínez; Antonio González 001 (HiPC, 2013)

Vectorizing for Wider Vector Units in a HW/SW Co-designed Environment. - Rakesh Kumar 003; Alejandro Martínez; Antonio González 001 (HPCC/EUC, 2013)

Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery. - Gaurang Upasani; Xavier Vera; Antonio González 001 (IOLTS, 2013)

Deconfigurable microprocessor architectures for silicon debug acceleration. - Nikos Foutris; Dimitris Gizopoulos; Xavier Vera; Antonio González 001 (ISCA, 2013)

Effectiveness of hybrid recovery techniques on parametric failures. - Shrikanth Ganapathy; Ramon Canal; Antonio González 001; Antonio Rubio 001 (ISQED, 2013)

Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment. - Rakesh Kumar 003; Alejandro Martínez; Antonio González 001 (SBAC-PAD, 2013)

Replacement techniques for dynamic NUCA cache designs on CMPs. - Javier Lira; Carlos Molina; Ryan N. Rakvic; Antonio González 001 (J. Supercomput., 2013)

Accurate off-line phase classification for HW/SW co-designed processors. - Aleksandar Brankovic; Kyriakos Stavrou; Enric Gibert; Antonio González 001 (Conf. Computing Frontiers, 2014)

Warm-Up Simulation Methodology for HW/SW Co-Designed Processors. - Aleksandar Brankovic; Kyriakos Stavrou; Enric Gibert; Antonio González 001 (CGO, 2014)

INFORMER: An integrated framework for early-stage memory robustness analysis. - Shrikanth Ganapathy; Ramon Canal; Dan Alexandrescu; Enrico Costenaro; Antonio González 001; Antonio Rubio 001 (DATE, 2014)

iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches. - Shrikanth Ganapathy; Ramon Canal; Antonio González 001; Antonio Rubio 001 (ICCD, 2014)

Author retrospective for the dual data cache. - Antonio González 001; Carlos Aliagas (ICS 25th Anniversary, 2014)

Cross-layer early reliability evaluation: Challenges and promises. - Stefano Di Carlo; Alessandro Vallero; Dimitris Gizopoulos; Giorgio Di Natale; Antonio González 001; Ramon Canal; Riccardo Mariani; M. Pipponzi; Arnaud Grasset; Philippe Bonnot 001; Frank Reichenbach; Gulzaib Rafiq; et al. (IOLTS, 2014)

Framework for economical error recovery in embedded cores. - Gaurang Upasani; Xavier Vera; Antonio González 001 (IOLTS, 2014)

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery. - Gaurang Upasani; Xavier Vera; Antonio González 001 (ISCA, 2014)

Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment. - Rakesh Kumar 003; Alejandro Martínez; Antonio González 001 (ACM Trans. Archit. Code Optim., 2014)

Chrysso: an integrated power manager for constrained many-core processors. - Sudhanshu Shekhar Jha; Wim Heirman; Ayose Falcón; Trevor E. Carlson; Kenzo Van Craeynest; Jordi Tubella; Antonio González 001; Lieven Eeckhout (Conf. Computing Frontiers, 2015)

Ultra-low power render-based collision detection for CPU/GPU systems. - Enrique de Lucas; Pedro Marcuello; Joan-Manuel Parcerisa; Antonio González 001 (MICRO, 2015)

Analysis and Optimization of Engines for Dynamically Typed Languages. - Gem Dot; Alejandro Martínez; Antonio González 001 (SBAC-PAD, 2015)

A detailed methodology to compute Soft Error Rates in advanced technologies. - Marc Riera; Ramon Canal; Jaume Abella 001; Antonio González 001 (DATE, 2016)

ERICO: Effective Removal of Inline Caching Overhead in Dynamic Typed Languages. - Gem Dot; Alejandro Martínez; Antonio González 001 (HiPC, 2016)

MASkIt: Soft error rate estimation for combinational circuits. - Martí Anglada; Ramon Canal; Juan L. Aragón; Antonio González 001 (ICCD, 2016)

Quantitative characterization of the software layer of a HW/SW co-designed processor. - José Cano 001; Rakesh Kumar 003; Aleksandar Brankovic; Demos Pavlou; Kyriakos Stavrou; Enric Gibert; Alejandro Martínez; Antonio González 001 (IISWC, 2016)

Cross-layer system reliability assessment framework for hardware faults. - Alessandro Vallero; Alessandro Savino; Gianfranco Politano; Stefano Di Carlo; Athanasios Chatzidimitriou; Sotiris Tselonis; Manolis Kaliorakis; Dimitris Gizopoulos; Marc Riera; Ramon Canal; Antonio González 001; Maha Kooli; et al. (ITC, 2016)

An ultra low-power hardware accelerator for automatic speech recognition. - Reza Yazdani; Albert Segura; José-María Arnau; Antonio González 001 (MICRO, 2016)

An Energy-Efficient Memory Unit for Clustered Microarchitectures. - Stefan Bieschewski; Joan-Manuel Parcerisa; Antonio González 001 (IEEE Trans. Computers, 2016)

A Case for Acoustic Wave Detectors for Soft-Errors. - Gaurang Upasani; Xavier Vera; Antonio González 001 (IEEE Trans. Computers, 2016)

Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment. - Rakesh Kumar 003; Alejandro Martínez; Antonio González 001 (ACM Trans. Comput. Syst., 2016)

Scalability of Broadcast Performance in Wireless Network-on-Chip. - Sergi Abadal; Albert Mestres; Mario Nemirovsky; Heekwan Lee; Antonio González 001; Eduard Alarcón; Albert Cabellos-Aparicio (IEEE Trans. Parallel Distributed Syst., 2016)

An Ultra Low-Power Hardware Accelerator for Acoustic Scoring in Speech Recognition. - Hamid Tabani; José-María Arnau; Jordi Tubella; Antonio González 001 (PACT, 2017)

Removing checks in dynamically typed languages through efficient profiling. - Gem Dot; Alejandro Martínez; Antonio González 001 (CGO, 2017)

MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment. - Manolis Kaliorakis; Dimitris Gizopoulos; Ramon Canal; Antonio González 001 (ISCA, 2017)

UNFOLD: a memory-efficient speech recognizer using on-the-fly WFST composition. - Reza Yazdani; José-María Arnau; Antonio González 001 (MICRO, 2017)

Shared resource aware scheduling on power-constrained tiled many-core processors. - Sudhanshu Shekhar Jha; Wim Heirman; Ayose Falcón; Jordi Tubella; Antonio González 001; Lieven Eeckhout (J. Parallel Distributed Comput., 2017)

Low-Power Automatic Speech Recognition Through a Mobile GPU and a Viterbi Accelerator. - Reza Yazdani; Albert Segura; José-María Arnau; Antonio González 001 (IEEE Micro, 2017)

E-PUR: an energy-efficient processing unit for recurrent neural networks. - Franyell Silfa; Gem Dot; José-María Arnau; Antonio González 001 (PACT, 2018)

A Novel Register Renaming Technique for Out-of-Order Processors. - Hamid Tabani; José-María Arnau; Jordi Tubella; Antonio González 001 (HPCA, 2018)

Computation Reuse in DNNs by Exploiting Input Similarity. - Marc Riera; José-María Arnau; Antonio González 001 (ISCA, 2018)

The Dark Side of DNN Pruning. - Reza Yazdani; Marc Riera; José-María Arnau; Antonio González 001 (ISCA, 2018)

Trends in Processor Architecture. - Antonio González 001 (CoRR, 2018)

2018 International Symposium on Computer Architecture Influential Paper Award. - Antonio González 001 (IEEE Micro, 2018)

Performance Analysis and Optimization of Automatic Speech Recognition. - Hamid Tabani; José-María Arnau; Jordi Tubella; Antonio González 001 (IEEE Trans. Multi Scale Comput. Syst., 2018)

POSTER: Leveraging Run-Time Feedback for Efficient ASR Acceleration. - Reza Yazdani; José-María Arnau; Antonio González 001 (PACT, 2019)

Early Visibility Resolution for Removing Ineffectual Computations in the Graphics Pipeline. - Martí Anglada; Enrique de Lucas; Joan-Manuel Parcerisa; Juan L. Aragón; Antonio González 001 (HPCA, 2019)

Rendering Elimination: Early Discard of Redundant Tiles in the Graphics Pipeline. - Martí Anglada; Enrique de Lucas; Joan-Manuel Parcerisa; Juan L. Aragón; Pedro Marcuello; Antonio González 001 (HPCA, 2019)

SCU: a GPU stream compaction unit for graph processing. - Albert Segura; José-María Arnau; Antonio González 001 (ISCA, 2019)

Neuron-Level Fuzzy Memoization in RNNs. - Franyell Silfa; Gem Dot; José-María Arnau; Antonio González 001 (MICRO, 2019)

(Pen-) Ultimate DNN Pruning. - Marc Riera; José-María Arnau; Antonio González 001 (CoRR, 2019)

LSTM-Sharp: An Adaptable, Energy-Efficient Hardware Accelerator for Long Short-Term Memory. - Reza Yazdani; Olatunji Ruwase; Minjia Zhang; Yuxiong He; José-María Arnau; Antonio González 001 (CoRR, 2019)

CGPA: Coarse-Grained Pruning of Activations for Energy-Efficient RNN Inference. - Marc Riera; José-María Arnau; Antonio González 001 (IEEE Micro, 2019)

SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems. - Alessandro Vallero; Alessandro Savino; Athanasios Chatzidimitriou; Manolis Kaliorakis; Maha Kooli; Marc Riera; Martí Anglada; Giorgio Di Natale; Alberto Bosio; Ramon Canal; Antonio González 001; Dimitris Gizopoulos; et al. (IEEE Trans. Computers, 2019)

A Low-Power, High-Performance Speech Recognition Accelerator. - Reza Yazdani; José-María Arnau; Antonio González 001 (IEEE Trans. Computers, 2019)

Visibility Rendering Order: Improving Energy Efficiency on Mobile GPUs through Frame Coherence. - Enrique de Lucas; Pedro Marcuello; Joan-Manuel Parcerisa; Antonio González 001 (IEEE Trans. Parallel Distributed Syst., 2019)

Boosting LSTM Performance Through Dynamic Precision Selection. - Franyell Silfa; José-María Arnau; Antonio González 001 (HiPC, 2020)

Demystifying Power and Performance Bottlenecks in Autonomous Driving Systems. - Pedro Henrique Exenberger Becker; José-María Arnau; Antonio González 001 (IISWC, 2020)

Design and Evaluation of an Ultra Low-power Human-quality Speech Recognition System. - Dennis Pinto; José-María Arnau; Antonio González 001 (ACM Trans. Archit. Code Optim., 2020)

LAWS: Locality-AWare Scheme for Automatic Speech Recognition. - Reza Yazdani; José-María Arnau; Antonio González 001 (IEEE Trans. Computers, 2020)

A Low-Power Hardware Accelerator for ORB Feature Extraction in Self-Driving Cars. - Raúl Taranco; José-María Arnau; Antonio González 001 (SBAC-PAD, 2021)

Exploiting Beam Search Confidence for Energy-Efficient Speech Recognition. - Dennis Pinto; José-María Arnau; Antonio González 001 (CoRR, 2021)

Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design. - Martí Anglada; Ramon Canal; Juan L. Aragón; Antonio González 001 (IEEE Trans. Sustain. Comput., 2021)

TCOR: A Tile Cache with Optimal Replacement. - Diya Joseph; Juan L. Aragón; Joan-Manuel Parcerisa; Antonio González 001 (HPCA, 2022)

XFeatur: Hardware Feature Extraction for DNN Auto-tuning. - Jorge Sierra Acosta; Andreas Diavastos; Antonio González 001 (ISPASS, 2022)

MEGsim: A Novel Methodology for Efficient Simulation of Graphics Workloads in GPUs. - Jorge Ortiz; David Corbalán-Navarro; Juan L. Aragón; Antonio González 001 (ISPASS, 2022)

DTexL: Decoupled Raster Pipeline for Texture Locality. - Diya Joseph; Juan L. Aragón; Joan-Manuel Parcerisa; Antonio González 001 (MICRO, 2022)

DTM-NUCA: Dynamic Texture Mapping-NUCA for Energy-Efficient Graphics Rendering. - David Corbalán-Navarro; Juan L. Aragón; Joan-Manuel Parcerisa; Antonio González 001 (PDP, 2022)

ASRPU: A Programmable Accelerator for Low-Power Automatic Speech Recognition. - Dennis Pinto; José-María Arnau; Antonio González 001 (CoRR, 2022)

Mixture-of-Rookies: Saving DNN Computations by Predicting ReLU Outputs. - Dennis Pinto; José-María Arnau; Antonio González 001 (CoRR, 2022)

Saving RNN Computations with a Neuron-Level Fuzzy Memoization Scheme. - Franyell Silfa; José-María Arnau; Antonio González 001 (CoRR, 2022)

DNN pruning with principal component analysis and connection importance estimation. - Marc Riera; José-María Arnau; Antonio González 001 (J. Syst. Archit., 2022)

CREW: Computation reuse and efficient weight storage for hardware-accelerated MLPs and RNNs. - Marc Riera; José-María Arnau; Antonio González 001 (J. Syst. Archit., 2022)

A Survey of Near-Data Processing Architectures for Neural Networks. - Mehdi Hassanpour; Marc Riera; Antonio González 001 (Mach. Learn. Knowl. Extr., 2022)

Triangle Dropping: An Occluded-geometry Predictor for Energy-efficient Mobile GPUs. - David Corbalán-Navarro; Juan L. Aragón; Martí Anglada; Joan-Manuel Parcerisa; Antonio González 001 (ACM Trans. Archit. Code Optim., 2022)

E-BATCH: Energy-Efficient and High-Throughput RNN Batching. - Franyell Silfa; José-María Arnau; Antonio González 001 (ACM Trans. Archit. Code Optim., 2022)

Energy-Efficient Stream Compaction Through Filtering and Coalescing Accesses in GPGPU Memory Partitions. - Albert Segura; José-María Arnau; Antonio González 001 (IEEE Trans. Computers, 2022)

Dynamic sampling rate: harnessing frame coherence in graphics applications for energy-efficient GPUs. - Martí Anglada; Enrique de Lucas; Joan-Manuel Parcerisa; Juan L. Aragón; Antonio González 001 (J. Supercomput., 2022)

Omega-Test: A Predictive Early-Z Culling to Improve the Graphics Pipeline Energy-Efficiency. - David Corbalán-Navarro; Juan L. Aragón; Martí Anglada; Enrique de Lucas; Joan-Manuel Parcerisa; Antonio González 001 (IEEE Trans. Vis. Comput. Graph., 2022)

Boustrophedonic Frames: Quasi-Optimal L2 Caching for Textures in GPUs. - Diya Joseph; Juan L. Aragón; Joan-Manuel Parcerisa; Antonio González 001 (PACT, 2023)

QeiHaN: An Energy-Efficient DNN Accelerator that Leverages Log Quantization in NDP Architectures. - Bahareh Khabbazan; Marc Riera; Antonio González 001 (PACT, 2023)

SLIDEX: Sliding Window Extension for Image Processing. - Raúl Taranco; José-María Arnau; Antonio González 001 (PACT, 2023)

Exploiting Kernel Compression on BNNs. - Franyell Silfa; José-María Arnau; Antonio González 001 (DATE, 2023)

Simple Out of Order Core for GPGPUs. - Rodrigo Huerta; José-María Arnau; Antonio González 001 (GPGPU@PPoPP, 2023)

Lightweight Register File Caching in Collector Units for GPUs. - Mojtaba Abaie Shoushtary; José-María Arnau; Jordi Tubella Murgadas; Antonio González 001 (GPGPU@PPoPP, 2023)

DNA-TEQ: An Adaptive Exponential Quantization of Tensors for DNN Inference. - Bahareh Khabbazan; Marc Riera; Antonio González 001 (HiPC, 2023)

K-D Bonsai: ISA-Extensions to Compress K-D Trees for Autonomous Driving Tasks. - Pedro Henrique Exenberger Becker; José-María Arnau; Antonio González 001 (ISCA, 2023)

δLTA: Decoupling Camera Sampling from Processing to Avoid Redundant Computations in the Vision Pipeline. - Raúl Taranco; José-María Arnau; Antonio González 001 (MICRO, 2023)

ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNN Inference. - Mohammad Sabri Abrebekoh; Marc Riera; Antonio González 001 (CoRR, 2023)

A Lightweight, Compiler-Assisted Register File Cache for GPGPU. - Mojtaba Abaie Shoushtary; José-María Arnau; Jordi Tubella Murgadas; Antonio González 001 (CoRR, 2023)

An Energy-Efficient Near-Data Processing Accelerator for DNNs that Optimizes Data Accesses. - Bahareh Khabbazan; Marc Riera; Antonio González 001 (CoRR, 2023)

ReuseSense: With Great Reuse Comes Greater Efficiency; Effectively Employing Computation Reuse on General-Purpose CPUs. - Nitesh Narayana GS; Marc Ordoñez; Lokananda Hari; Franyell Silfa; Antonio González 001 (CoRR, 2023)

Irregular accesses reorder unit: improving GPGPU memory coalescing for graph-based workloads. - Albert Segura; José-María Arnau; Antonio González 001 (J. Supercomput., 2023)

SHARP: An Adaptable, Energy-Efficient Accelerator for Recurrent Neural Networks. - Reza Yazdani Aminabadi; Olatunji Ruwase; Minjia Zhang; Yuxiong He; José-María Arnau; Antonio González 001 (ACM Trans. Embed. Comput. Syst., 2023)

LOCATOR: Low-power ORB accelerator for autonomous cars. - Raúl Taranco; José-María Arnau; Antonio González 001 (J. Parallel Distributed Comput., 2023)

ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNNs. - Mohammad Sabri Abrebekoh; Marc Riera Villanueva; Antonio González 001 (ICPP, 2024)

SLIDEX: A Novel Architecture for Sliding Window Processing. - Raúl Taranco; José-María Arnau; Antonio González 001 (ICS, 2024)

Memento: An Adaptive, Compiler-Assisted Register File Cache for GPUs. - Mojtaba Abaie Shoushtary; José-María Arnau; Jordi Tubella Murgadas; Antonio González 001 (ISCA, 2024)

LIBRA: Memory Bandwidth- and Locality-Aware Parallel Tile Rendering. - Aurora Tomás; Juan L. Aragón; Joan-Manuel Parcerisa; Antonio González 001 (MICRO, 2024)

Analyzing and Improving Hardware Modeling of Accel-Sim. - Rodrigo Huerta; Mojtaba Abaie Shoushtary; Antonio González 001 (CoRR, 2024)

WaSP: Warp Scheduling to Mimic Prefetching in Graphics Workloads. - Diya Joseph; Juan Luis Aragón; Joan-Manuel Parcerisa; Antonio González 001 (CoRR, 2024)

Control Flow Management in Modern GPUs. - Mojtaba Abaie Shoushtary; Jordi Tubella Murgadas; Antonio González 001 (CoRR, 2024)

ARAS: An Adaptive Low-Cost ReRAM-Based Accelerator for DNNs. - Mohammad Sabri; Marc Riera; Antonio González 001 (CoRR, 2024)

SIMIL: SIMple Issue Logic for GPUs. - Rodrigo Huerta; José-Lorenzo Cruz; José-María Arnau; Antonio González 001 (Microprocess. Microsystems, 2024)

Mixture-of-Rookies: Saving DNN computations by predicting ReLU outputs. - Dennis Pinto; José-María Arnau; Marc Riera; José-Lorenzo Cruz; Antonio González 001 (Microprocess. Microsystems, 2024)

Exploiting beam search confidence for energy-efficient speech recognition. - Dennis Pinto; José-María Arnau; Marc Riera; José-Lorenzo Cruz; Antonio González 001 (J. Supercomput., 2024)

IRIS: Unleashing ISP-Software Cooperation to Optimize the Machine Vision Pipeline. - Raúl Taranco; José-María Arnau; Antonio González 001 (HPCA, 2025)

Caravan: A Hardware/Software Co-Design for Efficient SIMD Neighbor Search on Point Clouds. - Pedro Henrique Exenberger Becker; Franyell Silfa; José-María Arnau; Antonio González 001 (ISCA, 2025)

GPU Simulation Acceleration via Parallelization. - Rodrigo Huerta; Antonio González 001 (ISPASS, 2025)

On the Development of Vehicle Dynamics Active Systems: The Handling Stability Ratio as a Strategic Indicator for Integrating Multiple Actuators. - Roberto Aratri; Stefano De Pinto; Giuseppe Guastadisegni; Antonio González 001; Aldo Sorniotti; Francesco Bottiglione; Giacomo Mantriota (IEEE Access, 2025)

An energy-efficient near-data processing accelerator for DNNs to optimize memory accesses. - Bahareh Khabbazan; Mohammad Sabri; Marc Riera; Antonio González 001 (J. Syst. Archit., 2025)

Hamun: An approximate computing method to prolong the lifespan of ReRAM-based accelerators. - Mohammad Sabri; Marc Riera; Antonio González 001 (J. Syst. Archit., 2025)

Hamun: An Approximate Computation Method to Prolong the Lifespan of ReRAM-Based Accelerators. - Mohammad Sabri; Marc Riera; Antonio González 001 (CoRR, 2025)

Towards Efficient LUT-based PIM: A Scalable and Low-Power Approach for Modern Workloads. - Bahareh Khabbazan; Marc Riera; Antonio González 001 (CoRR, 2025)

Parallelizing a modern GPU simulator. - Rodrigo Huerta; Antonio González 001 (CoRR, 2025)

Analyzing Modern NVIDIA GPU cores. - Rodrigo Huerta; Mojtaba Abaie Shoushtary; José-Lorenzo Cruz; Antonio González 001 (CoRR, 2025)