A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line. - Antonio H. Chan; Gordon W. Roberts (ITC, 2001)

A deep sub-micron timing measurement circuit using a single-stage Vernier delay line. - Antonio H. Chan; Gordon W. Roberts (CICC, 2002)

A High-Throughput 5 GBps Timing and Jitter Test Module Featuring Localized Processing. - Mohamed M. Hafed; Antonio H. Chan; Geoffrey D. Duerden; Bardia Pishdad; Clarence Tam; Sébastien Laberge; Gordon W. Roberts (ITC, 2004)

A jitter characterization system using a component-invariant Vernier delay line. - Antonio H. Chan; Gordon W. Roberts (IEEE Trans. Very Large Scale Integr. Syst., 2004)