Modeling of real bistables in VHDL. - Antonio J. Acosta 001; Angel Barriga; Manuel Valencia-Barrero; Manuel J. Bellido; José L. Huertas (EURO-DAC, 1993)

A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. - Manuel J. Bellido; Manuel Valencia-Barrero; Antonio J. Acosta 001; Angel Barriga; José Luis Huertas; Rafael Domínguez-Castro (ISCAS, 1993)

New CMOS VLSI linear self-timed architectures. - Antonio J. Acosta 001; Manuel J. Bellido; Manuel Valencia-Barrero; Angel Barriga; Raúl Jiménez; José L. Huertas (ASYNC, 1995)

Modular Asynchronous Arbiter Insensitive to Metastability. - Manuel Valencia-Barrero; Manuel J. Bellido; José L. Huertas; Antonio J. Acosta 001; Santiago Sánchez-Solano (IEEE Trans. Computers, 1995)

SODS: a new CMOS differential-type structure. - Antonio J. Acosta 001; Manuel Valencia 001; Angel Barriga; Manuel J. Bellido; José L. Huertas (IEEE J. Solid State Circuits, 1995)

Efficient self-timed circuits based on weak NMOS-trees. - Raúl Jiménez; Antonio J. Acosta 001; Angel Barriga; Manuel J. Bellido; Manuel Valencia 001 (ICECS, 1998)

Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. - T. A. García; Antonio J. Acosta 001; J. M. Mora; J. Ramos; José Luis Huertas (J. Electron. Test., 1999)

A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. - Eduardo J. Peralías; Antonio J. Acosta 001; Adoración Rueda; José L. Huertas (DATE, 2000)

Inertial and degradation delay model for CMOS logic gates. - Jorge Juan-Chico; Paulino Ruiz-de-Clavijo; Manuel J. Bellido; Antonio J. Acosta 001; Manuel Valencia 001 (ISCAS, 2000)

VHDL-based behavioural description of pipeline ADCs. - Eduardo J. Peralías; Antonio J. Acosta 001; Adoración Rueda; José L. Huertas (ISCAS, 2000)

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. - Antonio J. Acosta 001; Raúl Jiménez; Jorge Juan-Chico; Manuel J. Bellido; Manuel Valencia-Barrero (PATMOS, 2000)

An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. - Raúl Jiménez; Antonio J. Acosta 001; Eduardo J. Peralías; Adoración Rueda (PATMOS, 2000)

Degradation Delay Model Extension to CMOS Gates. - Jorge Juan-Chico; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; Antonio J. Acosta 001; Manuel Valencia-Barrero (PATMOS, 2000)

Analog/mixed-signal IP modeling for design reuse. - Natividad Martínez Madrid; Eduardo J. Peralías; Antonio J. Acosta 001; Adoración Rueda (DATE, 2001)

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. - Paulino Ruiz-de-Clavijo; Jorge Juan-Chico; Manuel J. Bellido; Antonio J. Acosta 001; Manuel Valencia-Barrero (DATE, 2001)

Gate-level simulation of CMOS circuits using the IDDM model. - Manuel J. Bellido; Jorge Juan-Chico; Paulino Ruiz-de-Clavijo; Antonio J. Acosta 001; Manuel Valencia-Barrero (ISCAS (5), 2001)

A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. - Raúl Jiménez; Pilar Parra Fernández; Pedro Sanmartín; Antonio J. Acosta 001 (PATMOS, 2002)

Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. - Pilar Parra Fernández; Antonio J. Acosta 001; Manuel Valencia-Barrero (PATMOS, 2002)

A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. - Raúl Jiménez; Pilar Parra Fernández; Pedro Sanmartín; Antonio J. Acosta 001 (PATMOS, 2003)

AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems. - Rafael Serrano-Gotarredona; Matthias Oster; Patrick Lichtsteiner; Alejandro Linares-Barranco; Rafael Paz-Vicente; Francisco Gomez-Rodriguez; Håvard Kolle Riis; Tobi Delbruck; Shih-Chii Liu; S. Zahnd; Adrian M. Whatley; Rodney J. Douglas; et al. (NIPS, 2005)

Selective Clock-Gating for Low-Power Synchronous Counters. - Pilar Parra Fernández; Antonio J. Acosta 001; Raúl Jiménez; Manuel Valencia-Barrero (J. Low Power Electron., 2005)

A mixed-signal integrated circuit for FM-DCSK modulation. - Manuel Delgado-Restituto; Antonio J. Acosta 001; Ángel Rodríguez-Vázquez (IEEE J. Solid State Circuits, 2005)

High-speed image processing with AER-based components. - Rafael Serrano-Gotarredona; Bernabé Linares-Barranco; Teresa Serrano-Gotarredona; Antonio Acosta-Jimenez; Alejandro Linares-Barranco; Rafael Paz-Vicente; Francisco Gomez-Rodriguez (ISCAS, 2006)

An arbitrary kernel convolution AER-transceiver chip for real-time image filtering. - Rafael Serrano-Gotarredona; Teresa Serrano-Gotarredona; Antonio Acosta-Jimenez; Bernabé Linares-Barranco (ISCAS, 2006)

Optimization of Master-Slave Flip-Flops for High-Performance Applications. - Raúl Jiménez; Pilar Parra Fernández; Javier Castro-Ramirez; Manuel Sanchez-Raya; Antonio J. Acosta 001 (PATMOS, 2006)

A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems. - Rafael Serrano-Gotarredona; Teresa Serrano-Gotarredona; Antonio Acosta-Jimenez; Bernabé Linares-Barranco (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A switching noise vision of the optimization techniques for low-power synthesis. - Javier Castro-Ramirez; Pilar Parra Fernández; Manuel Valencia-Barrero; Antonio J. Acosta 001 (ECCTD, 2007)

Asymmetric clock driver for improved power and noise performances. - Javier Castro-Ramirez; Pilar Parra Fernández; Manuel Valencia-Barrero; Antonio J. Acosta 001 (ISCAS, 2007)

Asynchronous Staggered Set/Reset Techniques for Low-Noise Applications. - Renato Rimolo-Donadio; Antonio J. Acosta 001; Wolfgang H. Krautschneider (ISCAS, 2007)

Spike Events Processing for Vision Systems. - Rafael Serrano-Gotarredona; Teresa Serrano-Gotarredona; Antonio Acosta-Jimenez; Alejandro Linares-Barranco; Gabriel Jiménez-Moreno; Antón Civit Balcells; Bernabé Linares-Barranco (ISCAS, 2007)

A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications. - Antonio Jose Ginés; Ricardo Doldán; Alberto Villegas; Antonio J. Acosta 001; Maria Angeles Jalón; Diego Vázquez; Adoración Rueda; Eduardo J. Peralías (APCCAS, 2008)

Fully digital AER convolution chip for vision processing. - Luis A. Camuñas-Mesa; Antonio Acosta-Jimenez; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (ISCAS, 2008)

On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing. - Rafael Serrano-Gotarredona; Teresa Serrano-Gotarredona; Antonio Acosta-Jimenez; Carmen Serrano-Gotarredona; José Antonio Pérez-Carrasco; Bernabé Linares-Barranco; Alejandro Linares-Barranco; Gabriel Jiménez-Moreno; Antón Civit Balcells (IEEE Trans. Neural Networks, 2008)

Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. - Javier Castro-Ramirez; Pilar Parra Fernández; Antonio J. Acosta 001 (PATMOS, 2009)

CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-Processing- Learning-Actuating System for High-Speed Visual Object Recognition and Tracking. - Rafael Serrano-Gotarredona; Matthias Oster; Patrick Lichtsteiner; Alejandro Linares-Barranco; Rafael Paz-Vicente; Francisco Gomez-Rodriguez; Luis A. Camuñas-Mesa; Raphael Berner; Manuel Rivas Pérez; Tobi Delbruck; Shih-Chii Liu; Rodney J. Douglas; et al. (IEEE Trans. Neural Networks, 2009)

Optimization of clock-gating structures for low-leakage high-performance applications. - Javier Castro-Ramirez; Pilar Parra Fernández; Antonio J. Acosta 001 (ISCAS, 2010)

A 32, times, 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput. - Luis A. Camuñas-Mesa; Antonio Acosta-Jimenez; Carlos Zamarreño-Ramos; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

ASIC-in-the-loop methodology for verification of piecewise affine controllers. - Macarena C. Martínez-Rodríguez; Piedad Brox; Javier Castro-Ramirez; Erica Tena; Antonio J. Acosta 001; Iluminada Baturone (ICECS, 2012)

An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors. - Luis A. Camuñas-Mesa; Carlos Zamarreño-Ramos; Alejandro Linares-Barranco; Antonio Acosta-Jimenez; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco (IEEE J. Solid State Circuits, 2012)

A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions. - Piedad Brox; Javier Castro-Ramirez; Macarena C. Martínez-Rodríguez; Erica Tena; Carlos Jesús Jiménez-Fernández; Iluminada Baturone; Antonio J. Acosta 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Low-Power Differential Logic Gates for DPA Resistant Circuits. - Erica Tena-Sánchez; Javier Castro-Ramirez; Antonio J. Acosta 001 (DSD, 2014)

Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications. - Erica Tena-Sánchez; Javier Castro-Ramirez; Antonio J. Acosta 001 (PATMOS, 2014)

A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits. - Erica Tena-Sánchez; Javier Castro-Ramirez; Antonio J. Acosta 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Programmable ASICs for model predictive control. - Macarena C. Martínez-Rodríguez; Piedad Brox; Erica Tena; Antonio J. Acosta 001; Iluminada Baturone (ICIT, 2015)

DPA vulnerability analysis on Trivium stream cipher using an optimized power model. - Erica Tena-Sánchez; Antonio J. Acosta 001 (ISCAS, 2015)

Secure cryptographic hardware implementation issues for high-performance applications. - Erica Tena-Sánchez; Antonio J. Acosta 001; Juan Núñez 002 (PATMOS, 2016)

Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions. - Piedad Brox; Macarena C. Martínez-Rodríguez; Erica Tena-Sánchez; Iluminada Baturone; Antonio J. Acosta 001 (Int. J. Circuit Theory Appl., 2016)

Guest Editorial "Secure lightweight crypto-hardware". - Antonio J. Acosta 001; Tommaso Addabbo (Int. J. Circuit Theory Appl., 2017)

Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview. - Antonio J. Acosta 001; Tommaso Addabbo; Erica Tena-Sánchez (Int. J. Circuit Theory Appl., 2017)

Power and Energy Issues on Lightweight Cryptography. - Antonio J. Acosta 001; Erica Tena-Sánchez; Carlos Jesús Jiménez-Fernández; Javier M. Mora-Merchan (J. Low Power Electron., 2017)

Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. - Erica Tena-Sánchez; Ignacio M. Delgado-Lozano; Juan Núñez 002; Antonio J. Acosta 001 (DCIS, 2018)

Effect of Temperature Variation in Experimental DPA and DEMA Attacks. - Erica Tena-Sánchez; Antonio J. Acosta 001 (PATMOS, 2018)

Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks. - Erica Tena-Sánchez; Antonio J. Acosta 001 (Int. J. Circuit Theory Appl., 2019)

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Ricardo Chaves; Manuel Valencia-Barrero; Antonio Acosta-Jiménez; Carlos Jesús Jiménez-Fernández (ISCAS, 2020)

Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies. - Ignacio M. Delgado-Lozano; Erica Tena-Sánchez; Juan Núñez 002; Antonio J. Acosta 001 (ACM J. Emerg. Technol. Comput. Syst., 2020)

Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices. - Ignacio M. Delgado-Lozano; Erica Tena-Sánchez; Juan Núñez 002; Antonio J. Acosta 001 (IEEE Trans. Emerg. Top. Comput., 2021)

Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Antonio J. Acosta 001; Carlos Jesús Jiménez-Fernández; Ricardo Chaves (IEEE Access, 2022)

Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs. - Ignacio M. Delgado-Lozano; Erica Tena-Sánchez; Juan Núñez 002; Antonio J. Acosta 001 (IEEE Embed. Syst. Lett., 2022)

A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks. - Virginia Zúñiga-González; Erica Tena-Sánchez; Antonio J. Acosta 001 (DCIS, 2023)

Cryptographic Security Through a Hardware Root of Trust. - Luis F. Rojas-Muñoz; Santiago Sánchez-Solano; Macarena C. Martínez-Rodríguez; Eros Camacho-Ruiz; Pablo Navarro-Torrero; Apurba Karmakar; Carlos Fernández García; Erica Tena-Sánchez; Francisco Eugenio Potestad-Ordóñez; Alejandro Casado-Galán; Pau Ortega-Castro; Antonio Acosta-Jiménez; et al. (ARC, 2024)

Electromagnetic Fault Injection Attack Methodology against AES Hardware Implementation. - Alejandro Casado-Galán; Francisco Eugenio Potestad-Ordóñez; Antonio J. Acosta 001; Erica Tena-Sánchez (DCIS, 2024)

Hardware implementations, SCA/FIA attacks, and countermeasures for the ASCON AEAD cipher: a review. - Miguel Martín-González; Erica Tena-Sánchez; F. Eugenio Potestad Ordóñez; Antonio J. Acosta 001 (DCIS, 2024)

Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Virginia Zúñiga-González; Antonio J. Acosta 001 (DSD, 2024)

TERORO - Transient Effect Ring Oscillator and Ring Oscillator Configurable Hybrid PUF. - Alejandro Casado-Galán; J. Núñez-Martínez; Erica Tena-Sánchez; Francisco Eugenio Potestad-Ordóñez; Antonio J. Acosta 001 (SMACD, 2025)