Antonio J. Acosta

Affiliations:
  • University of Sevilla, Spain


According to our database1, Antonio J. Acosta authored at least 54 papers between 1993 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2021
Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices.
IEEE Trans. Emerg. Top. Comput., 2021

2020
Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies.
ACM J. Emerg. Technol. Comput. Syst., 2020

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks.
Int. J. Circuit Theory Appl., 2019

2018
Effect of Temperature Variation in Experimental DPA and DEMA Attacks.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
Power and Energy Issues on Lightweight Cryptography.
J. Low Power Electron., 2017

Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview.
Int. J. Circuit Theory Appl., 2017

Guest Editorial "Secure lightweight crypto-hardware".
Int. J. Circuit Theory Appl., 2017

2016
Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions.
Int. J. Circuit Theory Appl., 2016

Secure cryptographic hardware implementation issues for high-performance applications.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

2015
DPA vulnerability analysis on Trivium stream cipher using an optimized power model.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Programmable ASICs for model predictive control.
Proceedings of the IEEE International Conference on Industrial Technology, 2015

2014
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Low-Power Differential Logic Gates for DPA Resistant Circuits.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors.
IEEE J. Solid State Circuits, 2012

ASIC-in-the-loop methodology for verification of piecewise affine controllers.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A 32, times, 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010
Optimization of clock-gating structures for low-leakage high-performance applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-Processing- Learning-Actuating System for High-Speed Visual Object Recognition and Tracking.
IEEE Trans. Neural Networks, 2009

Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2008
On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing.
IEEE Trans. Neural Networks, 2008

Fully digital AER convolution chip for vision processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Spike Events Processing for Vision Systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Asynchronous Staggered Set/Reset Techniques for Low-Noise Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Asymmetric clock driver for improved power and noise performances.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A switching noise vision of the optimization techniques for low-power synthesis.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Optimization of Master-Slave Flip-Flops for High-Performance Applications.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

An arbitrary kernel convolution AER-transceiver chip for real-time image filtering.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High-speed image processing with AER-based components.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Selective Clock-Gating for Low-Power Synchronous Counters.
J. Low Power Electron., 2005


2003
A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application.
Proceedings of the Integrated Circuit and System Design, 2003

2002
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2001
Gate-level simulation of CMOS circuits using the IDDM model.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Analog/mixed-signal IP modeling for design reuse.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Degradation Delay Model Extension to CMOS Gates.
Proceedings of the Integrated Circuit Design, 2000

An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits.
Proceedings of the Integrated Circuit Design, 2000

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits.
Proceedings of the Integrated Circuit Design, 2000

VHDL-based behavioural description of pipeline ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Inertial and degradation delay model for CMOS logic gates.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters.
Proceedings of the 2000 Design, 2000

1999
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test.
J. Electron. Test., 1999

1998
Efficient self-timed circuits based on weak NMOS-trees.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1995
Modular Asynchronous Arbiter Insensitive to Metastability.
IEEE Trans. Computers, 1995

New CMOS VLSI linear self-timed architectures.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

1993
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Modeling of real bistables in VHDL.
Proceedings of the European Design Automation Conference 1993, 1993


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