A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda; Ralf Seepold; Natividad Martínez Madrid (DATE, 2002)

Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (SBCCI, 2003)

Digital Background Gain Error Correction in Pipeline ADCs. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (DATE, 2004)

Full calibration digital techniques for pipeline ADCs. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (ISCAS (3), 2005)

Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (ISCAS, 2006)

Improved Background Algorithms for Pipeline ADC Full Calibration. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (ISCAS, 2007)

Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (SBCCI, 2007)

A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications. - Antonio Jose Ginés; Ricardo Doldán; Alberto Villegas; Antonio J. Acosta 001; Maria Angeles Jalón; Diego Vázquez; Adoración Rueda; Eduardo J. Peralías (APCCAS, 2008)

A 5GHz wide tuning range LC-VCO in sub-micrometer CMOS technology. - Ricardo Doldán Lorenzo; Antonio Jose Ginés Arteaga; Adoración Rueda; Eduardo J. Peralías (APCCAS, 2008)

On-line estimation of the integral non-linear errors in analogue-to-digital converters without histogram evaluation. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (ECCTD, 2009)

A survey on digital background calibration of ADCs. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (ECCTD, 2009)

Power optimization of CMOS programmable gain amplifiers with high dynamic range and common-mode feed-forward circuit. - Antonio J. Ginés; Ricardo Doldán; Adoración Rueda; Eduardo J. Peralías (ICECS, 2010)

On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation. - Antonio J. Ginés; Ricardo Doldán; Manuel J. Barragan Asian; Adoración Rueda; Eduardo J. Peralías (ISCAS, 2010)

On Chopper Effects in Discrete-Time SigmaDelta Modulators. - Gildas Léger; Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Blind Adaptive Estimation of Integral Nonlinear Errors in ADCs Using Arbitrary Input Stimulus. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (IEEE Trans. Instrum. Meas., 2011)

Self-biased input common-mode generation for improving dynamic range and yield in inverter-based filters. - Antonio Jose Ginés; Alberto Villegas; Eduardo J. Peralías; Adoración Rueda (ICECS, 2012)

Analysis of steady-state common-mode response in differential LC-VCOs. - Ricardo Doldán; Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (ISCAS, 2012)

Inductor characterization in RF LC-VCOs. - Ricardo Doldán; Antonio J. Ginés; Adoración Rueda (LASCAS, 2013)

Sigma-delta testability for pipeline A/D converters. - Antonio J. Ginés; Gildas Léger (DATE, 2014)

INL systematic reduced-test technique for Pipeline ADCs. - Eduardo J. Peralías; Antonio Jose Ginés; Adoración Rueda (ETS, 2014)

Closed-loop simulation method for evaluation of static offset in discrete-time comparators. - Antonio J. Ginés; Eduardo J. Peralías; Gildas Léger; Adoración Rueda (ICECS, 2014)

An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs. - Juan Núñez 002; Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (LASCAS, 2015)

Background Digital Calibration of Comparator Offsets in Pipeline ADCs. - Antonio Jose Ginés; Eduardo J. Peralías; Adoración Rueda (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications. - Manuel Delgado-Restituto; Manuel Carrasco-Robles; Rafaella Fiorelli; Antonio Jose Ginés Arteaga; Ángel Rodríguez-Vázquez (APCCAS, 2016)

Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. - Antonio J. Ginés; Eduardo J. Peralías; Gildas Léger; Adoración Rueda; Guillaume Renaud; Manuel J. Barragán; Salvador Mir (ETS, 2016)

On the limits of machine learning-based test: A calibrated mixed-signal system case study. - Manuel J. Barragán; Gildas Léger; Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (DATE, 2017)

Black-Box Calibration for ADCs With Hard Nonlinear Errors Using a Novel INL-Based Additive Code: A Pipeline ADC Case Study. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs. - Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Redundant SAR ADCs with Split-capacitor DAC. - Antonio Lopez-Angulo; Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (ICECS, 2018)

AMS-RF test quality: Assessing defect severity. - Valentin Guiterrez; Antonio J. Ginés; Gildas Léger (IOLTS, 2018)

Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach. - Antonio J. Ginés; Antonio Lopez-Angulo; Eduardo J. Peralías; Adoración Rueda (ISCAS, 2018)

Mismatch and Offset Calibration in Redundant SAR ADC. - Antonio Lopez-Angulo; Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (DCIS, 2019)

Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder. - Antonio Jose Ginés; Eduardo José Peralías; Cristina Aledo; Adoración Rueda (Int. J. Circuit Theory Appl., 2019)

On-chip reduced-code static linearity test of Vcm-based switching SAR ADCs using an incremental analog-to-digital converter. - Renato S. Feitoza; Manuel J. Barragán; Antonio J. Ginés; Salvador Mir (ETS, 2020)

Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy. - Antonio Lopez-Angulo; Antonio J. Ginés; Eduardo J. Peralías (ISCAS, 2020)

Fast Simulation of Non-Linear Circuits using Semi-Analytical Solutions Based on the Matrix Exponential. - J. A. Serrano; Antonio J. Ginés; Eduardo J. Peralías (ISCAS, 2020)

Static linearity BIST for Vcm-based switching SAR ADCs using a reduced-code measurement technique. - Renato S. Feitoza; Manuel J. Barragán; Antonio J. Ginés; Salvador Mir (NEWCAS, 2020)

Non-Linear Calibration of Pipeline ADCs using a Histogram-Based Estimation of the Redundant INL. - Antonio J. Ginés; Gildas Léger; Eduardo J. Peralías (NEWCAS, 2020)

Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy. - Antonio Lopez-Angulo; Antonio J. Ginés; Eduardo J. Peralías (NEWCAS, 2020)

Digital Non-Linearity Calibration for ADCs With Redundancy Using a New LUT Approach. - Antonio J. Ginés; Gildas Léger; Eduardo J. Peralías (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A methodology for defect detection in analog circuits based on causal feature selection. - Gildas Léger; Antonio J. Ginés; Valentin Gutierrez; Manuel J. Barragán (ICECS 2022, 2022)

A Single-Event Latchup setup for high-precision AMS circuits. - Gildas Léger; Antonio J. Ginés; Eduardo J. Peralías; Valentin Gutierrez; Carlos M. Domínguez-Matas; Maria Angeles Jalón; L. Carranza (ETS, 2023)

Behavioral Model for High-Speed SAR ADCs With On-Chip References. - Carlos Manuel Domínguez-Matas; Antonio J. Ginés; Aránzazu Otín; Valentin Gutierrez; Gildas Léger; Eduardo J. Peralías (IEEE Trans. Very Large Scale Integr. Syst., 2023)

On the Validity of SEE Simulation for Rad-Hard Analog ASICs. - Valentin Gutierrez; Carlos M. Domínguez-Matas; Gildas Léger; Antonio J. Ginés; Eduardo J. Peralías (IOLTS, 2025)