A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures. - Mauro Olivieri; Antonio Mastrandrea (VLSI Design, 2013)

Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops. - Usman Khalid; Antonio Mastrandrea; Mauro Olivieri (DSD, 2014)

A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs. - Zia Abbas; Antonio Mastrandrea; Mauro Olivieri (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs. - Mauro Olivieri; Antonio Mastrandrea (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops. - Usman Khalid; Antonio Mastrandrea; Mauro Olivieri (Microelectron. Reliab., 2015)

An Emulator for Approximate Memory Platforms Based on QEmu. - Francesco Menichelli; Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri (ApplePies, 2016)

The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes. - Abdallah Cheikh; Gianmarco Cerutti; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (ApplePies, 2017)

Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores. - Mauro Olivieri; Abdallah Cheikh; Gianmarco Cerutti; Antonio Mastrandrea; Francesco Menichelli (NGCAS, 2017)

Approximate Memory Support for Linux Early Allocators in ARM Architectures. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (ApplePies, 2018)

Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing. - Giulia Stazi; Federica Silvestri; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (ApplePies, 2018)

Characterizing noise pulse effects on the power consumption of idle digital cells. - Mauro Olivieri; Usman Khalid; Antonio Mastrandrea; Francesco Menichelli (ISCAS, 2018)

AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (NGCAS, 2018)

Impact of Approximate Memory Data Allocation on a H.264 Software Video Encoder. - Giulia Stazi; Lorenzo Adani; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (ISC Workshops, 2018)

A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer. - Luigi Blasi; Francesco Vigli; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (ApplePies, 2019)

Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor. - Abdallah Cheikh; Stefano Sordillo; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (ApplePies, 2019)

Quality Aware Selective ECC for Approximate DRAM. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (ApplePies, 2019)

On the Simulation and Automatic Parametrization of Metabolic Networks Through Electronic Design Automation. - Nicola Bombieri; Antonio Mastrandrea; Silvia Scaffeo; Simone Caligola; Franco Fummi; Carlo Laudanna; Gabriela Constantin; Rosalba Giugno (CIBB, 2019)

A PULP-based Parallel Power Controller for Future Exascale Systems. - Andrea Bartolini; Davide Rossi; Antonio Mastrandrea; Christian Conficoni; Simone Benatti; Andrea Tilli; Luca Benini (ICECS, 2019)

Quality Aware Approximate Memory in RISC-V Linux Kernel. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (PRIME, 2019)

Full System Emulation of Approximate Memory Platforms with AppropinQuo. - Giulia Stazi; Antonio Mastrandrea; Mauro Olivieri; Francesco Menichelli (J. Low Power Electron., 2019)

Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment. - Marcello Barbirotta; Antonio Mastrandrea; Francesco Menichelli; Francesco Vigli; Luigi Blasi; Abdallah Cheikh; Stefano Sordillo; Fabio Di Gennaro; Mauro Olivieri (DFT, 2020)

Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores. - Abdallah Cheikh; Stefano Sordillo; Antonio Mastrandrea; Francesco Menichelli; Giuseppe Scotti; Mauro Olivieri (CoRR, 2020)

A Ladder Network Theoretical Approach for the Automatic Monitoring of Distributed Sensors. - Alessandro Zompanti; Anna Sabatini; Simone Grasso; Giorgio Pennazza; Antonio Mastrandrea; Giuseppe Ferri; Gianluca Barile; Marco Santonico (AISEM, 2021)

A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. - Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Francesco Vigli; Mauro Olivieri (DFT, 2021)

Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores. - Abdallah Cheikh; Stefano Sordillo; Antonio Mastrandrea; Francesco Menichelli; Giuseppe Scotti; Mauro Olivieri (IEEE Micro, 2021)

SystemC Implementation of Stochastic Petri Nets for Simulation and Parameterization of Biological Networks. - Nicola Bombieri; Silvia Scaffeo; Antonio Mastrandrea; Simone Caligola; Tommaso Carlucci; Franco Fummi; Carlo Laudanna; Gabriela Constantin; Rosalba Giugno (ACM Trans. Embed. Comput. Syst., 2021)

3D-Printed Face Mask with Integrated Sensors as Protective and Monitoring Tool. - Silvia Casalinuovo; Alessio Buzzin; Antonio Mastrandrea; Ivan Mazzetta; Marcello Barbirotta; Lorenzo Iannascoli; Augusto Nascetti; Giampiero de Cesare; Donatella Puglisi; Domenico Caputo (AISEM, 2022)

Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators. - Marco Angioli; Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Saeid Jamili; Mauro Olivieri (ApplePies, 2022)

Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor. - Saeid Jamili; Abdallah Cheikh; Antonio Mastrandrea; Marcello Barbirotta; Francesco Menichelli; Marco Angioli; Mauro Olivieri (ApplePies, 2022)

Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration. - Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (PRIME, 2022)

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors. - Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (IEEE Access, 2022)

Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design. - Marcello Barbirotta; Marco Angioli; Antonio Mastrandrea; Abdallah Cheikh; Saeid Jamili; Francesco Menichelli; Mauro Olivieri (ApplePies, 2023)

Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects. - Marcello Barbirotta; Francesco Menichelli; Antonio Mastrandrea; Abdallah Cheikh; Marco Angioli; Saeid Jamili; Mauro Olivieri (ApplePies, 2023)

A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach. - Saeid Jamili; Antonio Mastrandrea; Abdallah Cheikh; Marcello Barbirotta; Francesco Menichelli; Marco Angioli; Mauro Olivieri (ApplePies, 2023)

Automatic Hardware Accelerators Reconfiguration through LinearUCB Algorithms on a RISC-V Processor. - Marco Angioli; Marcello Barbirotta; Antonio Mastrandrea; Saeid Jamili; Mauro Olivieri (PRIME, 2023)

Alternative Implementations of Error Correcting Codes in Register Files of a RISC-V Safety Critical Processor. - Marcello Barbirotta; Marco Angioli; Antonio Mastrandrea; Abdallah Cheikh; Francesco Menichelli; Mauro Olivieri (ApplePies, 2024)

Special Session: SE-UVM, an Integrated Simulation Environment for Single Event Induced Failures Characterization and its Application to the CV32E40P Processor. - Marcello Barbirotta; Marco Angioli; Antonio Mastrandrea; Francesco Menichelli; Abdallah Cheikh; Mauro Olivieri (DFT, 2024)

Dual-Modular-Redundancy Voting Circuits for Single-Event-Transient Mitigation. - Marcello Barbirotta; Marco Angioli; Antonio Mastrandrea; Francesco Menichelli; Abdallah Cheikh; Mauro Olivieri (DFT, 2024)

AeneasHDC: An Automatic Framework for Deploying Hyperdimensional Computing Models on FPGAs. - Marco Angioli; Saeid Jamili; Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Antonello Rosato; Mauro Olivieri (IJCNN, 2024)

Exploring Variable Latency Dividers in Vector Hardware Accelerators. - Marco Angioli; Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Mauro Olivieri (PRIME, 2024)

Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems. - Marcello Barbirotta; Francesco Menichelli; Abdallah Cheikh; Antonio Mastrandrea; Marco Angioli; Mauro Olivieri (IEEE Access, 2024)

A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection. - Francesco Vigli; Marcello Barbirotta; Abdallah Cheikh; Francesco Menichelli; Antonio Mastrandrea; Mauro Olivieri (IEEE Access, 2024)

A Simple Microwave Imaging System for Food Product Inspection through a Symmetry-Based Microwave Imaging Approach. - Gennaro Bellizzi; Alessio Buzzin; Lorenzo Crocco; Antonio Mastrandrea; Noemi Zeni; Sabrina Zumbo; Marta Cavagnaro (Sensors, 2024)

Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme. - Marco Angioli; Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Saeid Jamili; Mauro Olivieri (IEEE Trans. Computers, 2024)

Efficient Implementation of LinearUCB through Algorithmic Improvements and Vector Computing Acceleration for Embedded Learning Systems. - Marco Angioli; Marcello Barbirotta; Abdallah Cheikh; Antonio Mastrandrea; Francesco Menichelli; Mauro Olivieri (ACM Trans. Embed. Comput. Syst., 2025)