Design SRAMs for burn-in. - William R. Reohr; Yuen H. Chan; Donald W. Plass; Antonio Pelella; Philip T. Wu (VTS, 1993)

The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA). - William V. Huott; Moyra K. McManus; Daniel R. Knebel; Steve Steen; Dennis Manzer; Pia N. Sanda; Steven C. Wilson; Yuen H. Chan; Antonio Pelella; Stanislav Polonsky (ITC, 1999)

A 8Kb domino read SRAM with hit logic and parity checker. - Antonio Pelella; Arthur Tuminaro; Ryan T. Freese; Yuen H. Chan (ESSCIRC, 2005)

A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. - John Davis; Don Plass; Paul Bunce; Yuen H. Chan; Antonio Pelella; Rajiv V. Joshi; A. Chen; William V. Huott; Thomas J. Knips; Pradip Patel; K. Lo; Eric Fluhr (ISSCC, 2006)

Dynamic hit logic with embedded 8Kb SRAM in 45nm SOI for the zEnterprise™ processor. - Antonio Pelella; Yuen H. Chan; Bargav Balakrishnan; Pradip Patel; Daniel Rodko; Richard E. Serton (ISSCC, 2011)

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System. - James D. Warnock; Yiu-Hing Chan; Sean M. Carey; Huajun Wen; Patrick J. Meaney; Guenter Gerwig; Howard H. Smith; Yuen H. Chan; John Davis; Paul Bunce; Antonio Pelella; Daniel Rodko; et al. (IEEE J. Solid State Circuits, 2012)