Fault tolerance overhead in network-on-chip flow control schemes. - Antonio Pullini; Federico Angiolini; Davide Bertozzi; Luca Benini (SBCCI, 2005)

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips. - Srinivasan Murali; Rutuparna Tamhankar; Federico Angiolini; Antonio Pullini; David Atienza; Luca Benini; Giovanni De Micheli (SoC, 2006)

Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. - Andrea Calimera; Antonio Pullini; Ashoka Visweswara Sathanur; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2007)

Timing-driven row-based power gating. - Ashoka Visweswara Sathanur; Antonio Pullini; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (ISLPED, 2007)

NoC Design and Implementation in 65nm Technology. - Antonio Pullini; Federico Angiolini; Paolo Meloni; David Atienza; Srinivasan Murali; Luigi Raffo; Giovanni De Micheli; Luca Benini (NOCS, 2007)

Bringing NoCs to 65 nm. - Antonio Pullini; Federico Angiolini; Srinivasan Murali; David Atienza; Giovanni De Micheli; Luca Benini (IEEE Micro, 2007)

Timing-Error-Tolerant Network-on-Chip Design Methodology. - Rutuparna Tamhankar; Srinivasan Murali; Stergios Stergiou; Antonio Pullini; Federico Angiolini; Luca Benini; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A Scalable Algorithmic Framework for Row-Based Power-Gating. - Ashoka Visweswara Sathanur; Antonio Pullini; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (DATE, 2008)

Optimal sleep transistor synthesis under timing and area constraints. - Ashoka Visweswara Sathanur; Antonio Pullini; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2008)

On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. - Ashoka Visweswara Sathanur; Andrea Calimera; Antonio Pullini; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (ISCAS, 2008)

Network-on-Chip design and synthesis outlook. - David Atienza; Federico Angiolini; Srinivasan Murali; Antonio Pullini; Luca Benini; Giovanni De Micheli (Integr., 2008)

Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis. - Shashikanth Bobba; Jie Zhang 007; Antonio Pullini; David Atienza; Giovanni De Micheli (DATE, 2009)

Physically clustered forward body biasing for variability compensation in nanometer CMOS design. - Ashoka Visweswara Sathanur; Antonio Pullini; Luca Benini; Giovanni De Micheli; Enrico Macii (DATE, 2009)

A floorplan-aware interactive tool flow for NoC design and synthesis. - Mohammad Reza Kakoee; Federico Angiolini; Srinivasan Murali; Antonio Pullini; Ciprian Seiculescu; Luca Benini (SoCC, 2009)

Networks on Chips: from research to products. - Giovanni De Micheli; Ciprian Seiculescu; Srinivasan Murali; Luca Benini; Federico Angiolini; Antonio Pullini (DAC, 2010)

3D NoCs - Unifying inter & intra chip communication. - Igor Loi; Pol Marchal; Antonio Pullini; Luca Benini (ISCAS, 2010)

Automatic synthesis of near-threshold circuits with fine-grained performance tunability. - Mohammad Reza Kakoee; Ashoka Visweswara Sathanur; Antonio Pullini; Jos Huisken; Luca Benini (ISLPED, 2010)

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. - Geert Van der Plas; Paresh Limaye; Igor Loi; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Vladimir Cherman; et al. (IEEE J. Solid State Circuits, 2011)

Row-based FBB: A design-time optimization for post-silicon tunable circuits. - Mohammad Reza Kakoee; Ashoka Visweswara Sathanur; Antonio Pullini; Luca Benini (Microelectron. J., 2012)

Sub-mW reconfigurable interface IC for electrochemical sensing. - Sara S. Ghoreishizadeh; Cristina Boero; Antonio Pullini; Camilla Baj-Rossi; Sandro Carrara; Giovanni De Micheli (BioCAS, 2014)

A lightweight cryptographic system for implantable biosensors. - Sara S. Ghoreishizadeh; Tolga Yalçin; Antonio Pullini; Giovanni De Micheli; Wayne P. Burleson; Sandro Carrara (BioCAS, 2014)

Brain-Inspired Classroom Occupancy Monitoring on a Low-Power Mobile Platform. - Francesco Conti 001; Antonio Pullini; Luca Benini (CVPR Workshops, 2014)

Energy-efficient vision on the PULP platform for ultra-low power parallel computing. - Francesco Conti 001; Davide Rossi; Antonio Pullini; Igor Loi; Luca Benini (SiPS, 2014)

PULP: A parallel ultra low power platform for next generation IoT applications. - Davide Rossi; Francesco Conti 001; Andrea Marongiu; Antonio Pullini; Igor Loi; Michael Gautschi; Giuseppe Tagliavini; Alessandro Capotondi; Philippe Flatresse; Luca Benini (Hot Chips Symposium, 2015)

Exploring architectural heterogeneity in intelligent vision systems. - Nandhini Chandramoorthy; Giuseppe Tagliavini; Kevin M. Irick; Antonio Pullini; Siddharth Advani; Sulaiman Al Habsi; Matthew Cotter; John Sampson; Vijaykrishnan Narayanan; Luca Benini (HPCA, 2015)

Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores. - Michael Gautschi; Andreas Traber; Antonio Pullini; Luca Benini; Michele Scandale; Alessandro Di Federico; Michele Beretta 002; Giovanni Agosta (VLSI-SoC, 2015)

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Fady Abouzeid; et al. (COOL Chips, 2016)

A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision. - Antonio Pullini; Francesco Conti 001; Davide Rossi; Igor Loi; Michael Gautschi; Luca Benini (ISCAS, 2016)

A Dual Processor Energy-Efficient Platform with Multi-core Accelerator for Smart Sensing. - Antonio Pullini; Stefan Mach; Michele Magno; Luca Benini (S-CUBE, 2016)

PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision. - Francesco Conti 001; Davide Rossi; Antonio Pullini; Igor Loi; Luca Benini (J. Signal Process. Syst., 2016)

Energy Efficient System for Tactile Data Decoding Using an Ultra-Low Power Parallel Platform. - Michele Magno; Ali Ibrahim; Antonio Pullini; Maurizio Valle; Luca Benini (NGCAS, 2017)

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology. - Alfio Di Mauro; Davide Rossi; Antonio Pullini; Philippe Flatresse; Luca Benini (PATMOS, 2017)

μDMA: An autonomous I/O subsystem for IoT end-nodes. - Antonio Pullini; Davide Rossi; Germain Haugou; Luca Benini (PATMOS, 2017)

Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications. - Pasquale Davide Schiavone; Francesco Conti 001; Davide Rossi; Michael Gautschi; Antonio Pullini; Eric Flamand; Luca Benini (PATMOS, 2017)

A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors. - Davide Rossi; Igor Loi; Antonio Pullini; Thomas Christoph Müller; Andreas Burg 001; Francesco Conti 001; Luca Benini; Philippe Flatresse (IEEE Des. Test, 2017)

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Philippe Flatresse; et al. (IEEE Micro, 2017)

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. - Francesco Conti 001; Robert Schilling; Pasquale Davide Schiavone; Antonio Pullini; Davide Rossi; Frank Kagan Gürkaynak; Michael Muehlberghuber; Michael Gautschi; Igor Loi; Germain Haugou; Stefan Mangard; Luca Benini (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices. - Michael Gautschi; Pasquale Davide Schiavone; Andreas Traber; Igor Loi; Antonio Pullini; Davide Rossi; Eric Flamand; Frank K. Gürkaynak; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2017)

GAP-8: A RISC-V SoC for AI at the Edge of the IoT. - Eric Flamand; Davide Rossi; Francesco Conti 001; Igor Loi; Antonio Pullini; Florent Rotenberg; Luca Benini (ASAP, 2018)

Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing. - Antonio Pullini; Davide Rossi; Igor Loi; Alfio Di Mauro; Luca Benini (ESSCIRC, 2018)

Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology. - Alfio Di Mauro; Davide Rossi; Antonio Pullini; Philippe Flatresse; Luca Benini (ISCAS, 2018)

An Energy Efficient E-Skin Embedded System for Real-Time Tactile Data Decoding. - Michele Magno; Ali Ibrahim; Antonio Pullini; Maurizio Valle; Luca Benini (J. Low Power Electron., 2018)

A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing. - Antonio Pullini; Francesco Conti 001; Davide Rossi; Igor Loi; Michael Gautschi; Luca Benini (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

An Energy Efficient System for Touch Modality Classification in Electronic Skin Applications. - Mario Osta; Ali Ibrahim; Michele Magno; Manuel Eggimann; Antonio Pullini; Paolo Gastaldo; Maurizio Valle (ISCAS, 2019)

Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing. - Antonio Pullini; Davide Rossi; Igor Loi; Giuseppe Tagliavini; Luca Benini (IEEE J. Solid State Circuits, 2019)

Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI. - Alfio Di Mauro; Davide Rossi; Antonio Pullini; Philippe Flatresse; Luca Benini (CoRR, 2020)

Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI. - Alfio Di Mauro; Davide Rossi; Antonio Pullini; Philippe Flatresse; Luca Benini (Integr., 2020)

MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. - Matheus A. Cavalcante; Samuel Riedel; Antonio Pullini; Luca Benini (DATE, 2021)

4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Stefan Mach; Alfio Di Mauro; Marco Guermandi; Giuseppe Tagliavini; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (ISSCC, 2021)

Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Alfio Di Mauro; Giuseppe Tagliavini; Stefan Mach; Marco Guermandi; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (CoRR, 2021)

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Alfio Di Mauro; Giuseppe Tagliavini; Stefan Mach; Marco Guermandi; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (IEEE J. Solid State Circuits, 2022)