Logic masking for SET Mitigation Using Approximate Logic Circuits. - Antonio Sanchez-Clemente; Luis Entrena; Mario García-Valderas; Celia López-Ongil (IOLTS, 2012)

Error masking with approximate logic circuits using dynamic probability estimations. - Antonio Sanchez-Clemente; Luis Entrena; Mario García-Valderas (IOLTS, 2014)

Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches. - Antonio Sanchez-Clemente; Luis Entrena; Radek Hrbacek; Lukás Sekanina (IEEE Trans. Reliab., 2016)

Approximate TMR for selective error mitigation in FPGAs based on testability analysis. - Antonio Sanchez-Clemente; Luis Entrena; Fernanda Lima Kastensmidt (AHS, 2018)

Improving approximate-TMR using multi-objective optimization genetic algorithm. - Iuri Albandes Cunha Gomes; Alejandro Serrano-Cases; Antonio J. Sanchez-Clemente; Mayler G. A. Martins; Antonio Martínez-Álvarez; Sergio Cuenca-Asensi; Fernanda Lima Kastensmidt (LATS, 2018)

Formal Verification of Fault-Tolerant Hardware Designs. - Luis Entrena; Antonio J. Sanchez-Clemente; Luis Ángel García-Astudillo; Marta Portela-García; Mario García-Valderas; Almudena Lindoso; Roberto Sarmiento (IEEE Access, 2023)

Removing Data Dependencies in the CCSDS 123.0-B-2 Predictor Weight Updating. - Yubal Barrios; Joan Bartrina-Rapesta; Miguel Hernández-Cabronero; Antonio Sanchez-Clemente; Ian Blanes; Joan Serra-Sagristà; Roberto Sarmiento (IEEE Geosci. Remote. Sens. Lett., 2024)