Detectability Dependency on Test Generation Process for Interconnection Opens. - Antonio Zenteno; Víctor H. Champac; Joan Figueras (LATW, 2000)

Detectability Conditions for Interconnection Open Defect. - Víctor H. Champac; Antonio Zenteno (VTS, 2000)

Resistive Opens in a Class of CMOS Latches: Analysis and DFT. - Antonio Zenteno; Víctor H. Champac (VTS, 2001)

Detectability Conditions of Full Opens in the Interconnections. - Antonio Zenteno; Víctor H. Champac; Joan Figueras (J. Electron. Test., 2001)

Behavior Analysis and Testing of Resistive Opens in the Clock Circuitry of Memory Elements. - Antonio Zenteno; Víctor H. Champac; Jaime Ramírez-Angulo (LATW, 2002)

Analysis and Attenuation Proposal in Ground Bounce. - Antonio Zenteno; Víctor H. Champac; Michel Renovell; Florence Azaïs (Asian Test Symposium, 2004)

Testing of resistive opens in CMOS latches and flip-flops. - Víctor H. Champac; Antonio Zenteno; José L. Garcia (ETS, 2005)

Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. - Antonio Zenteno Ramírez; Guillermo Espinosa; Víctor H. Champac (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Power distribution network analysis using semi irregular plane shape approach and via modeling. - Antonio Zenteno Ramírez (LATS, 2015)