Antonio Zenteno Ramírez

According to our database, Antonio Zenteno Ramírez authored at least 9 papers between 2000 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Power distribution network analysis using semi irregular plane shape approach and via modeling.

Antonio Zenteno Ramírez

Proceedings of the 16th Latin-American Test Symposium, 2015

2007

Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops.

Antonio Zenteno Ramírez, Guillermo Espinosa, Víctor H. Champac

IEEE Trans. Very Large Scale Integr. Syst., 2007

2005

Testing of resistive opens in CMOS latches and flip-flops.

Víctor H. Champac, Antonio Zenteno, José L. Garcia

Proceedings of the 10th European Test Symposium, 2005

2004

Analysis and Attenuation Proposal in Ground Bounce.

Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2002

Behavior Analysis and Testing of Resistive Opens in the Clock Circuitry of Memory Elements.

Antonio Zenteno, Víctor H. Champac, Jaime Ramírez-Angulo

Proceedings of the 3rd Latin American Test Workshop, 2002

2001

Detectability Conditions of Full Opens in the Interconnections.

Antonio Zenteno, Víctor H. Champac, Joan Figueras

J. Electron. Test., 2001

Resistive Opens in a Class of CMOS Latches: Analysis and DFT.

Antonio Zenteno, Víctor H. Champac

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000

Detectability Conditions for Interconnection Open Defect.

Víctor H. Champac, Antonio Zenteno

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Detectability Dependency on Test Generation Process for Interconnection Opens.

Antonio Zenteno, Víctor H. Champac, Joan Figueras

Proceedings of the 1st Latin American Test Workshop, 2000