Interconnect exploration for future wire dominated technologies. - Antonis Papanikolaou; Miguel Miranda; Francky Catthoor; Henk Corporaal; Hugo De Man; David De Roest; Michele Stucchi; Karen Maex (SLIP, 2002)

Global interconnect trade-off for technology over memory modules to application level: case study. - Antonis Papanikolaou; Miguel Miranda; Francky Catthoor; Henk Corporaal; Hugo De Man; David De Roest; Michele Stucchi; Karen Maex (SLIP, 2003)

A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement. - Hua Wang; Antonis Papanikolaou; Miguel Miranda; Francky Catthoor (ASP-DAC, 2004)

Overcoming the "Memory Wall" by improved system design exploration and a link to process technology options. - Antonis Papanikolaou; Miguel Miranda; Francky Catthoor (Conf. Computing Frontiers, 2004)

A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications. - Antonis Papanikolaou; F. Lobmaier; Hua Wang; Miguel Miranda; Francky Catthoor (CODES+ISSS, 2005)

Architectural and Physical Design Optimizations for Efficient Intra-tile Communication. - Antonis Papanikolaou; F. Starzer; Miguel Miranda; Koenraad De Bosschere; Francky Catthoor (SoC, 2005)

Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs. - Hua Wang; Miguel Miranda; Antonis Papanikolaou; Francky Catthoor; Wim Dehaene (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture. - Kris Heyrman; Antonis Papanikolaou; Francky Catthoor; Peter Veelaert; Koen De Bosschere; Wilfried Philips (ARC, 2006)

Physical design implementation of segmented buses to reduce communication energy. - Jin Guo 001; Antonis Papanikolaou; Pol Marchal; Francky Catthoor (ASP-DAC, 2006)

Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations. - Antonis Papanikolaou; T. Grabner; Miguel Miranda; Philippe Roussel; Francky Catthoor (CODES+ISSS, 2006)

System-level process variability compensation on memory organizations of dynamic applications: a case study. - Concepción Sanz; Manuel Prieto 001; Antonis Papanikolaou; Miguel Miranda; Francky Catthoor (ISQED, 2006)

Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture. - Jin Guo 001; Antonis Papanikolaou; Pol Marchal; Francky Catthoor (SLIP, 2006)

Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design. - Antonis Papanikolaou; Miguel Miranda; Hua Wang; Francky Catthoor; M. Satyakiran; Pol Marchal; Ben Kaczer; C. Bruynseraede; Zsolt Tokei (VLSI-SoC, 2006)

Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design. - Antonis Papanikolaou; Hua Wang; Miguel Miranda; Francky Catthoor; Wim Dehaene (VLSI-SoC (Selected Papers), 2006)

Topology exploration for energy efficient intra-tile communication. - Jin Guo 001; Antonis Papanikolaou; Francky Catthoor (ASP-DAC, 2007)

At Tape-out: Can System Yield in Terms of Timing/Energy Specifications Be Predicted? - Antonis Papanikolaou; Miguel Miranda; Pol Marchal; Bart Dierickx; Francky Catthoor (CICC, 2007)

Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design. - Antonis Papanikolaou; Hua Wang; Miguel Miranda; Francky Catthoor (IOLTS, 2007)

Using a Linear Sectioned Bus And a Communication Processor to Reduce Energy Costs in Synchronous On-Chip Communication. - Kris Heyrman; Antonis Papanikolaou; Francky Catthoor; Peter Veelaert; Wilfried Philips (SoC, 2007)

Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture. - Jin Guo 001; Antonis Papanikolaou; H. Zhang; Francky Catthoor (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A tool flow for predicting system level timing failures due to interconnect reliability degradation. - Jin Guo 001; Antonis Papanikolaou; Michele Stucchi; Kristof Croes; Zsolt Tokei; Francky Catthoor (ACM Great Lakes Symposium on VLSI, 2008)

Combining system scenarios and configurable memories to tolerate unpredictability. - Concepción Sanz; Manuel Prieto 001; José Ignacio Gómez; Antonis Papanikolaou; Miguel Miranda; Francky Catthoor (ACM Trans. Design Autom. Electr. Syst., 2008)

System-level process variability compensation on memory organizations: on the scalability of multi-mode memories. - Concepción Sanz; Manuel Prieto 001; José Ignacio Gómez; Antonis Papanikolaou; Francky Catthoor (ASP-DAC, 2009)

3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot. - Paul Marchal; Bruno Bougard; Guruprasad Katti; Michele Stucchi; Wim Dehaene; Antonis Papanikolaou; Diederik Verkest; Bart Swinnen; Eric Beyne (Proc. IEEE, 2009)

Fast Design Space Exploration Environment Applied on NoC's for 3D-Stacked MPSoC's. - Alienor Richard; Dragomir Milojevic; Frédéric Robert; Alexandros Bartzas; Antonis Papanikolaou; Kostas Siozios; Dimitrios Soudris (ARCS Workshops, 2010)

BIT-width exploration over 3D architectures using high-level synthesis. - Ioannis Koutras; Antonis Papanikolaou; George Economakos; Dimitrios Soudris (ICECS, 2010)

A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework. - Dimitris Bekiaris; Antonis Papanikolaou; Christos Papameletis; Dimitrios Soudris; George Economakos; Kiamal Z. Pekmestzi (PATMOS, 2010)

Control for Power Gating of Wires. - Kris Heyrman; Antonis Papanikolaou; Francky Catthoor; Peter Veelaert; Wilfried Philips (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm. - Filippos Toufexis; Antonis Papanikolaou; Dimitrios Soudris; George I. Stamoulis; Sotiris Bantas (ICECS, 2011)

CAD tools for designing 3D integrated systems. - Kostas Siozios; Antonis Papanikolaou; Dimitrios Soudris (ISCAS, 2011)

Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios. - Nikolaos Zompakis; Antonis Papanikolaou; Praveen Raghavan; Dimitrios Soudris; Francky Catthoor (SiPS, 2011)

Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems. - Grigorios Lyras; Dimitrios Rodopoulos; Antonis Papanikolaou; Dimitrios Soudris (DATE, 2013)

Accelerating All-to-All Protein Structures Comparison with TMalign Using a NoC Many-Cores Processor Architecture. - Anuj Sharma; Antonis Papanikolaou; Elias S. Manolakos (IPDPS Workshops, 2013)

Enabling Efficient System Configurations for Dynamic Wireless Applications Using System Scenarios. - Nikolaos Zompakis; Antonis Papanikolaou; Praveen Raghavan; Dimitrios Soudris; Francky Catthoor (Int. J. Wirel. Inf. Networks, 2013)

Combined Visual Comfort and Energy Efficiency through True Personalization of Automated Lighting Control. - Christos Malavazos; Antonis Papanikolaou; Konstantinos Tsatsakis; E. Hatzoplaki (SMARTGREENS, 2015)

Open system for energy services (OS4ES): An EU-funded research project to establish a non-discriminatory, multivendor-capability service delivery platform for smart grid services. - Jörg Benze; Andreas Lang; Antonis Papanikolaou; Tim Dethlefs; Wolfgang Renz; Andrea Schröder (SmartGridComm, 2015)

Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations. - Dimitrios Rodopoulos; Georgia Psychou; Mohamed M. Sabry; Francky Catthoor; Antonis Papanikolaou; Dimitrios Soudris; Tobias G. Noll; David Atienza (ACM Comput. Surv., 2015)

Demonstrating HW-SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane. - Dimitrios Rodopoulos; Antonis Papanikolaou; Francky Catthoor; Dimitrios Soudris (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Optimized Consumer-Centric Demand Response. - Konstantinos Tzanidakis; Christos Malavazos; Kostas Tsatsakis; Antonis Papanikolaou; Tasos Tsitsanis; Brendan O'Flynn (GIoTS, 2018)