Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. - Anu Asokan; Aida Todri-Sanial; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (DDECS, 2014)

A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. - Anu Asokan; Aida Todri-Sanial; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (ISVLSI, 2014)

An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. - Anu Asokan; Alberto Bosio; Arnaud Virazel; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch (ISVLSI, 2015)

A Signal-Integrity Aware ATPG Flow to Generate High-Quality Patterns for Testing System-on-Chip Designs. - Anu Asokan (VLSI-SoC, 2022)