A 2 GHz 3.1 mW type-I digital ring-based PLL. - Zule Xu; Anugerah Firdauzi; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2016)

A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC. - Anugerah Firdauzi; Zule Xu; Masaya Miyahara; Akira Matsuzawa (ISCAS, 2016)

High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator. - Anugerah Firdauzi; Zule Xu; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2017)

A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS. - Jian Sen Teh; Liter Siek; Abdel Martinez Alonso; Anugerah Firdauzi; Akira Matsuzawa (ISCAS, 2018)

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector. - Zule Xu; Anugerah Firdauzi; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2019)