Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. - Edith Beigné; Alexandre Valentian; Bastien Giraud; Olivier Thomas; Thomas Benoist; Yvain Thonnart; Serge Bernard; Guillaume Moritz; Olivier Billoint; Y. Maneglia; Philippe Flatresse; Jean-Philippe Noel; et al. (DATE, 2013)

Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology. - Guillaume Moritz; Bastien Giraud; Jean-Philippe Noel; David Turgis; Anuj Grover (ICICDT, 2013)

27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. - Robin Wilson; Edith Beigné; Philippe Flatresse; Alexandre Valentian; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; Anuj Grover; et al. (ISSCC, 2014)

Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs. - Anuj Grover; Promod Kumar; Mohammad Daud; G. S. Visweswaran; Chittoor R. Parthasarathy; Jean-Philippe Noel; David Turgis; Bastien Giraud; Guillaume Moritz (ICICDT, 2015)

Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems. - Gaurav Narang; Alexander Fell; Prakhar Raj Gupta; Anuj Grover (SoCC, 2015)

Area compact 5T portless SRAM cell for high density cache in 65nm CMOS. - Jitendra Yadav; Pallavi Das; Abhinav Jain; Anuj Grover (VDAT, 2015)

Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance. - Gaurav Narang; Pragya Sharma; Mansi Jain; Anuj Grover (VLSID, 2015)

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. - Edith Beigné; Alexandre Valentian; Ivan Miro Panades; Robin Wilson; Philippe Flatresse; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; et al. (IEEE J. Solid State Circuits, 2015)

Scan Chain Adaptation through ECO. - Jasvir Singh; Anuj Grover; Mausumi Pohit; Anurag Singh Baghel; Gurjit Kaur; Shalini Pathak (ATS, 2016)

Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques. - Nidhi Batra; Pawan Sehgal; Shashwat Kaushik; Mohammad S. Hashmi; Sudesh Bhalla; Anuj Grover (ACM Great Lakes Symposium on VLSI, 2016)

A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementation. - Nidhi Batra; Shashwat Kaushik; Anil Kumar Gundu; Mohammad S. Hashmi; G. S. Visweswaran; Anuj Grover (SoCC, 2016)

Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework. - Prakhar Raj Gupta; G. S. Visweswaran; Gaurav Narang; Anuj Grover (SoCC, 2016)

An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI. - Nidhi Batra; Anil Kumar Gundu; Mohammad S. Hashmi; G. S. Visweswaran; Anuj Grover (VDAT, 2016)

New stable loadless 6T dual-port SRAM cell design. - Antara Ganguly; Sangeeta Goyal; Sneha Bhatia; Anuj Grover (VDAT, 2016)

A New Sense Amplifier Topology with Improved Performance for High Speed SRAM Applications. - Anil Kumar Gundu; Mohammad S. Hashmi; Anuj Grover (VLSID, 2016)

Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies. - Anand Ilakal; Anuj Grover (VDAT, 2017)

A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. - Anuj Grover; G. S. Visweswaran; Chittoor R. Parthasarathy; Mohammad Daud; David Turgis; Bastien Giraud; Jean-Philippe Noel; Ivan Miro Panades; Guillaume Moritz; Edith Beigné; Philippe Flatresse; Promod Kumar; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

LoCCo-Based Scan Chain Stitching for Low-Power DFT. - Shalini Pathak; Anuj Grover; Mausumi Pohit; Nitin Bansal (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP Technology. - Ankush Mamgain; Anuj Grover (SoCC, 2018)

A 800MHz, O.21pJ, 1.2V to 6V Level Shifter Using Thin Gate Oxide Devices in 65nm LSTP. - Prakhar Shukla; Prabhat Singh; Tushar Maheshwari; Anuj Grover; Vikas Rana (ICECS, 2020)

Diagnostic Circuit for Latent Fault Detection in SRAM Row Decoder. - Shivendra Singh; Varshita Gupta; Anuj Grover; Kedar Janardan Dhori (ISQED, 2020)

Design & Benchmark of Single Bit & Multi Bit Sequential Elements in 65nm for Low Standby Power Consumption. - Shashank Neeraj Dwivedi; Ashish Kumar Seth; Anuj Grover (VDAT, 2020)

A 0.47V-1.17V 32KB Timing Speculative SRAM in 28nm HKMG CMOS. - Mishal Kumar; Anuj Grover; Vivek Dikshit; Varshita Gupta (VDAT, 2020)

A 0.9V 64Mb 6T SRAM cell with Read and Write assist schemes in 65nm LSTP technology. - Aparna Mishra; Anuj Grover (VDAT, 2020)

Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology. - Vaibhav Verma; Fiza Akhtar; Anuj Grover (VDAT, 2020)

Design of Sense Amplifier for Wide Voltage Range Operation of Split Supply Memories in 22nm HKMG CMOS Technology. - Vinay Patil; Anuj Grover; Anuj Parashar (VLSID, 2020)

Process Compensated Diagnostic Circuit For Impending Fault Detection In SRAM Write Drivers. - Swapnil Bansal; Anuj Grover (APCCAS, 2021)

Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS. - Mukesh Kumar Srivastav; Rimjhim; Govind Soni; Umang Mittal; Rupali Tewari; Riya Yadav; Anuj Grover; Kedar Janardan Dhori; Harsh Rawat (ICECS, 2021)

Reduced March iC- Test for Detecting Ageing Induced Faults in Memory Address Decoders. - Kumari Anjali; Shubham Saha; Anuj Grover (VLSID, 2021)

A 0.4µA Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-Volatile Memories in 65nm LSTP Technology. - Feraj Husain; Belal Iqbal; Anuj Grover (VLSID, 2021)

ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices. - Mohammed Aamir; Somya Sharma; Anuj Grover (IEEE Open J. Circuits Syst., 2021)

A Process and Data Variations Tolerant Capacitive Coupled 10T1C SRAM for In-Memory Compute (IMC) in Deep Neural Network Accelerators. - Belal Iqbal; Anuj Grover; Harsh Rawat (AICAS, 2022)

Up to 13.7% Increase in Throughput of RISC V SoC Using Timing Speculative Razor SRAM. - Srikrishna Vasudev; Kartickraj K; Anuj Grover (APCCAS, 2022)

Human Pose Estimation using Deep Learning Techniques. - Anant Grover; Deepak Arora; Anuj Grover (ICIMMI, 2022)

Keypoint Detection for Identifying Body Joints using TensorFlow. - Anuj Grover; Deepak Arora; Anant Grover (ICIMMI, 2022)

3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS. - Mukesh Kumar Srivastav; Rimjhim; Roshan Mishra; Anuj Grover; Kedar Janardan Dhori; Harsh Rawat (ISCAS, 2022)

Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI. - Chandan Kumar; Rahul Kumar; Anuj Grover; Shouri Chatterjee; Kedar Janardan Dhori; Harsh Rawat (VLSID, 2022)

A Sense Amplifier Based Bulk Built-In Current Sensor for Detecting Laser-Induced Currents. - Debjit Batabyal; Sandeep Kumar Singh; Rajnish Kumar Mishra; Anuj Grover (VLSID, 2023)

A Common Mode Insensitive Process Tolerant Sense Amplifier Design for In Memory Compute Applications in 65nm LSTP Technology. - Belal Iqbal; Anuj Grover; Harsh Rawat (VLSID, 2023)

Temperature-Resilient Ring Oscillator Design: Achieving Frequency Stability Across Voltage Domains. - Anuja Goyal; Divin Dominic; Anuj Grover (ICM, 2024)

Design Of High-Density Iso-Stable Asymmetric Memory Cell With Upto 10X Reduced Leakage. - Ajay Shroti; Anuj Grover (ISCAS, 2024)

0.6 to 1.2V Wide Voltage Range Bandgap Reference Generator in 18nm UTBB-FD-SOI Technology. - Tanisha Gupta; Shubham Jain; Anuj Grover (iSES, 2024)

Up to 45% Faster Supply Boosted Voltage Sense Amplifier (SBVSA) for High-Speed SRAMs. - Rachit Sharma; Anuj Grover; Ajay Shroti; Shouri Chatterjee (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

AnalogSim: a Modeling Framework for SRAM-based Analog In-Memory Computing. - Talha Bin Aslam; Anuj Grover; Harsh Rawat (ISCAS, 2025)