Flexible resource allocation and management for application graphs on ReNÉ MPSoC. - Kavitha T. Madhu; Anuj Rao; Saptarsi Das; Krishna C. Madhava; S. K. Nandy 001; Ranjani Narayan (PARMA-DITAM@HiPEAC, 2016)

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. - Scott Davidson 004; Shaolin Xie; Christopher Torng; Khalid Al-Hawaj; Austin Rovinski; Tutu Ajayi; Luis Vega; Chun Zhao; Ritchie Zhao; Steve Dai; Aporva Amarnath; Bandhav Veluri; et al. (IEEE Micro, 2018)

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. - Austin Rovinski; Chun Zhao; Khalid Al-Hawaj; Paul Gao 001; Shaolin Xie; Christopher Torng; Scott Davidson 004; Aporva Amarnath; Luis Vega; Bandhav Veluri; Anuj Rao; Tutu Ajayi; et al. (VLSI Circuits, 2019)