Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. - Anuja Sehgal; Vikram Iyengar; Mark D. Krasniewski; Krishnendu Chakrabarty (DAC, 2003)

Yield analysis for repairable embedded memories. - Anuja Sehgal; Aishwarya Dubey; Erik Jan Marinissen; Clemens Wouters; Harald P. E. Vranken; Krishnendu Chakrabarty (ETW, 2003)

TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers. - Anuja Sehgal; Sule Ozev; Krishnendu Chakrabarty (ICCAD, 2003)

Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures. - Anuja Sehgal; Krishnendu Chakrabarty (DATE, 2004)

IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. - Anuja Sehgal; Sandeep Kumar Goel; Erik Jan Marinissen; Krishnendu Chakrabarty (ITC, 2004)

SOC test planning using virtual test access architectures. - Anuja Sehgal; Vikram Iyengar; Krishnendu Chakrabarty (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores. - Anuja Sehgal; Fang Liu 029; Sule Ozev; Krishnendu Chakrabarty (DATE, 2005)

Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs. - Anuja Sehgal; Krishnendu Chakrabarty (ICCAD, 2005)

A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs. - Anuja Sehgal; Sule Ozev; Krishnendu Chakrabarty (ICCD, 2005)

Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. - Anuja Sehgal; Sandeep Kumar Goel; Erik Jan Marinissen; Krishnendu Chakrabarty (DATE, 2006)

Test infrastructure design for mixed-signal SOCs with wrapped analog cores. - Anuja Sehgal; Sule Ozev; Krishnendu Chakrabarty (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Test cost reduction for the AMD™ Athlon processor using test partitioning. - Anuja Sehgal; Jeff Fitzgerald; Jeff Rearick (ITC, 2007)

Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs. - Anuja Sehgal; Krishnendu Chakrabarty (IEEE Trans. Computers, 2007)

Test Access Mechanism for Multiple Identical Cores. - Grady Giles; Jing Wang; Anuja Sehgal; Kedarnath J. Balakrishnan; James Wingfield (ITC, 2008)

Power-aware SoC test planning for effective utilization of port-scalable testers. - Anuja Sehgal; Sudarshan Bahukudumbi; Krishnendu Chakrabarty (ACM Trans. Design Autom. Electr. Syst., 2008)

Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. - Ozgur Sinanoglu; Erik Jan Marinissen; Anuja Sehgal; Jeff Fitzgerald; Jeff Rearick (IEEE Des. Test Comput., 2009)

Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. - Sandeep Kumar Goel; Erik Jan Marinissen; Anuja Sehgal; Krishnendu Chakrabarty (IEEE Trans. Computers, 2009)