Design of a Low Leakage, Low Power and High Performance Search and Read Memory Using CAM and SRAM. - Anup Dandapat; D. Kayal; D. Mukhopadhyay (J. Low Power Electron., 2008)

Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications. - Prabir Saha; Arindam Banerjee 003; Partha Bhattacharyya; Anup Dandapat (ISED, 2011)

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics. - Prabir Saha; Arindam Banerjee 003; Anup Dandapat; Partha Bhattacharyya (Microelectron. J., 2011)

Design of High Speed Vedic Multiplier for Decimal Number System. - Prabir Saha; Arindam Banerjee 003; Anup Dandapat; Partha Bhattacharyya (VDAT, 2012)

Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications. - Prabir Saha; Deepak Kumar; Partha Bhattacharyya; Anup Dandapat (ISED, 2013)

A Novel Design of Seven Segment Decoder Using Cyclic Combinational Technique. - D. Ghosh; P. C. Mondal; D. Kayal; Partha Bhattacharyya; Anup Dandapat (J. Low Power Electron., 2013)

Improved matrix multiplier design for high-speed digital signal processing applications. - Prabir Saha; Arindam Banerjee 003; Partha Bhattacharyya; Anup Dandapat (IET Circuits Devices Syst., 2014)

Design of 64-Bit Squarer Based on Vedic Mathematics. - Prabir Saha; Deepak Kumar; Partha Bhattacharyya; Anup Dandapat (J. Circuits Syst. Comput., 2014)

Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique. - D. Kayal; Posiba Mostafa; Anup Dandapat; Chandan Kumar Sarkar (J. Signal Process. Syst., 2014)

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit. - Partha Bhattacharyya; Bijoy Kundu; Sovan Ghosh; Vinay Kumar; Anup Dandapat (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Design Methodology for Multiple Output Combinational Circuits Using Cyclic Combinational Technique. - Vinay Kumar; Anup Dandapat (J. Circuits Syst. Comput., 2016)

A Novel Methodology for Design of Cyclic Combinational Circuits. - Vinay Kumar; Chandan Kumar Jha 001; Gaurav Thapa; Anup Dandapat (J. Low Power Electron., 2016)

A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications. - Sandeep Mishra; Telajala Venkata Mahendra; Anup Dandapat (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control. - Sandeep Mishra; Anup Dandapat (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access. - Venkatesh Mani Tripathi; Sandeep Mishra; Jyotishman Saikia; Anup Dandapat (VLSID, 2017)

Energy-Efficient Adaptive Match-Line Controller for Large-Scale Associative Storage. - Sandeep Mishra; Anup Dandapat (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Self-Controlled High-Performance Precharge-Free Content-Addressable Memory. - Telajala Venkata Mahendra; Sandeep Mishra; Anup Dandapat (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme. - Sandeep Mishra; Telajala Venkata Mahendra; Jyotishman Saikia; Anup Dandapat (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory. - Sheikh Wasmir Hussain; Telajala Venkata Mahendra; Sandeep Mishra; Anup Dandapat (IEEE Trans. Consumer Electron., 2018)

A Low-Power Split-Controlled Single Ended Storage Content Addressable Memory. - Telajala Venkata Mahendra; Sheikh Wasmir Hussain; Sandeep Mishra; Anup Dandapat (iSES, 2019)

Low discharge precharge free matchline structure for energy-efficient search using CAM. - Telajala Venkata Mahendra; Sheikh Wasmir Hussain; Sandeep Mishra; Anup Dandapat (Integr., 2019)

The analogy of matchline sensing techniques for content addressable memory (CAM). - Sandeep Mishra; Telajala Venkata Mahendra; Sheikh Wasmir Hussain; Anup Dandapat (IET Comput. Digit. Tech., 2020)

Low-power content addressable memory design using two-layer P-N match-line control and sensing. - Sheikh Wasmir Hussain; Telajala Venkata Mahendra; Sandeep Mishra; Anup Dandapat (Integr., 2020)

A Novel Low-Power Matchline Evaluation Technique for Content Addressable Memory (CAM). - Telajala Venkata Mahendra; Sheikh Wasmir Hussain; Sandeep Mishra; Anup Dandapat (J. Inf. Sci. Eng., 2020)

Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications. - Telajala Venkata Mahendra; Sheikh Wasmir Hussain; Sandeep Mishra; Anup Dandapat (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Match-line control unit for power and delay reduction in hybrid CAM. - Sheikh Wasmir Hussain; Telajala Venkata Mahendra; Sandeep Mishra; Anup Dandapat (IET Circuits Devices Syst., 2021)

Design of a 1.29-1.61GHz LC-VCO with Improved Phase Noise and Figure-of-Merit (FoMT) for GPS and Satellite Navigation. - Keshab Das; Anup Dandapat; Sanjay Kumar Jana (J. Circuits Syst. Comput., 2022)

SMS-CAM: Shared matchline scheme for content addressable memory. - Sheikh Wasmir Hussain; Telajala Venkata Mahendra; Sandeep Mishra; Anup Dandapat (Integr., 2023)

Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine. - Sheikh Wasmir Hussain; Telajala Venkata Mahendra; Sandeep Mishra; Anup Dandapat (Integr., 2024)