Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application. - Yee William Li; George Patounakis; Anup P. Jose; Kenneth L. Shepard; Steven M. Nowick (ASYNC, 2003)

An on-chip jitter measurement circuit with sub-picosecond resolution. - Keith A. Jenkins; Anup P. Jose; David F. Heidel (ESSCIRC, 2005)

On-Chip Spectrum Analyzer for Analog Built-In Self Test. - Anup P. Jose; Keith A. Jenkins; Scott K. Reynolds (VTS, 2005)

Distributed Loss Compensation for Low-latency On-chip Interconnects. - Anup P. Jose; Kenneth L. Shepard (ISSCC, 2006)

Pulsed current-mode signaling for nearly speed-of-light intrachip communication. - Anup P. Jose; George Patounakis; Kenneth L. Shepard (IEEE J. Solid State Circuits, 2006)

Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication. - Anup P. Jose; Kenneth L. Shepard (IEEE J. Solid State Circuits, 2007)

A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs. - Jafar Savoj; Kenny C.-H. Hsieh; Fu-Tai An; J. Gong; Jay Im; Xuewen Jiang; Anup P. Jose; Vassili Kireev; Siok-Wei Lim; Arianne Roldan; D. Z. Turker; Parag Upadhyaya; et al. (IEEE J. Solid State Circuits, 2013)

Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS. - Jafar Savoj; Hesam Amir Aslanzadeh; Declan Carey; Marc Erett; Wayne Fang; Yohan Frans; Kenny C.-H. Hsieh; Jay Im; Anup P. Jose; Didem Turker; Parag Upadhyaya; Zhaoyin Daniel Wu; et al. (CICC, 2014)

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS. - Parag Upadhyaya; Jafar Savoj; Fu-Tai An; Ade Bekele; Anup P. Jose; Bruce Xu; Zhaoyin Daniel Wu; Didem Turker; Hesam Amir Aslanzadeh; Hiva Hedayati; Jay Im; Siok-Wei Lim; et al. (ISSCC, 2015)

A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS. - Yohan Frans; Declan Carey; Marc Erett; Hesam Amir Aslanzadeh; Wayne Y. Fang; Didem Turker; Anup P. Jose; Adebabay Bekele; Jay Im; Parag Upadhyaya; Zhaoyin Daniel Wu; Kenny C.-H. Hsieh; et al. (IEEE J. Solid State Circuits, 2015)

A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process. - Anup P. Jose; Valentin Abramzon; Mohamed Elzeftawi; Michael Wang; Kyunglok Kim; Younghoon Song; Shiva Moballegh; Jalil Kamali; Amir Amirkhany (CICC, 2019)

A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process. - Tianyu Wang 006; Da Wei; Ranick Ng; Gaurav Malhotra; Anup P. Jose; Amir Amirkhany; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2022)

A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop. - Mohamed Badr Younis; Mostafa Gamal Ahmed; Tianyu Wang 006; Ahmed E. AbdelRahman; Mahmoud A. Khalil; Anup P. Jose; Pavan Kumar Hanumolu (VLSI Technology and Circuits, 2023)