Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation. - Ritu Singhal; Asha Balijepalli; Anupama R. Subramaniam; Frank Liu 001; Sani R. Nassif; Yu Cao 001 (DAC, 2007)

Design rule optimization of regular layout for leakage reduction in nanoscale design. - Anupama R. Subramaniam; Ritu Singhal; Chi-Chao Wang; Yu Cao (ASP-DAC, 2008)

Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation. - Ritu Singhal; Asha Balijepalli; Anupama R. Subramaniam; Chi-Chao Wang; Frank Liu 001; Sani R. Nassif; Yu Cao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

An analytical approach to efficient circuit variability analysis in scaled CMOS design. - Samatha Gummalla; Anupama R. Subramaniam; Yu Cao 001; Chaitali Chakrabarti (ISQED, 2012)

Leakage reduction through optimization of regular layout parameters. - Anupama R. Subramaniam; Ritu Singhal; Chi-Chao Wang; Yu Cao (Microelectron. J., 2012)

Finite-point method for efficient timing characterization of sequential elements. - Anupama R. Subramaniam; Janet Roveda; Yu Cao 001 (Integr., 2015)

A Finite-Point Method for Efficient Gate Characterization Under Multiple Input Switching. - Anupama R. Subramaniam; Janet Roveda; Yu Cao 001 (ACM Trans. Design Autom. Electr. Syst., 2015)