Fast and accurate parasitic capacitance models for layout-aware. - Anuradha Agarwal; Hemanth Sampath; Veena Yelamanchili; Ranga Vemuri (DAC, 2004)

Accurate Estimation of Parasitic Capacitances in Analog Circuits. - Anuradha Agarwal; Hemanth Sampath; Veena Yelamanchili; Ranga Vemuri (DATE, 2004)

Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. - Mukesh Ranjan; Wim Verhaegen; Anuradha Agarwal; Hemanth Sampath; Ranga Vemuri; Georges G. E. Gielen (DATE, 2004)

A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. - Raoul F. Badaoui; Hemanth Sampath; Anuradha Agarwal; Ranga Vemuri (ACM Great Lakes Symposium on VLSI, 2004)

Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits. - Anuradha Agarwal; Glenn Wolfe; Ranga Vemuri (ACM Great Lakes Symposium on VLSI, 2005)

Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. - Anuradha Agarwal; Ranga Vemuri (ICCAD, 2005)

Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. - Anuradha Agarwal; Ranga Vemuri (ICCD, 2005)

Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams. - Huiying Yang; Anuradha Agarwal; Ranga Vemuri (ISVLSI, 2005)

Energy Efficiency of Microring Resonator (MRR)-Based Binary Decision Diagram (BDD) Circuits. - Ozan Yakar; Yuqi Nie; Kazumi Wada; Anuradha Agarwal; Ilke Ercan (ICRC, 2019)

6-channel CMOS-based instrument for optical absorption spectroscopy and chemical identification. - Francesco Zanetto; Katherine Stoll; Samuel Serna; Anuradha Agarwal; Marco Sampietro; Giorgio Ferrari (ISCAS, 2023)