MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-$V_{th}$ Computing. - Anuradha Chathuranga Ranasinghe; Sabih H. Gerez (ICCD, 2020)

Ultra-Low Voltage 4-to-2 Compressors for Near-Vth Computing. - Anuradha Chathuranga Ranasinghe; Sabih H. Gerez (ISCAS, 2020)

Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers. - Anuradha Chathuranga Ranasinghe; Sabih H. Gerez (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Novel Ultra-Low-Voltage Flip-Flops: Near-Vth Modeling and VLSI Integration. - Anuradha Chathuranga Ranasinghe; Sabih H. Gerez (ICCD, 2021)

Ultra-Low-Voltage Flip-Flops and Near-Threshold Modeling. - Anuradha Chathuranga Ranasinghe (IEEE DataPort, 2022)

Gate-Level RTL Description of the Glitch Optimized Multipliers. - Anuradha Chathuranga Ranasinghe; Sabih H. Gerez (IEEE DataPort, 2022)

DET Flip Flop Usage with Commercial Cad Tools (Synthesis, P&R and Cell Characterization). - Anuradha Chathuranga Ranasinghe (IEEE DataPort, 2024)