Anuradha Chathuranga Ranasinghe

Orcid: 0000-0003-3352-0670

According to our database1, Anuradha Chathuranga Ranasinghe authored at least 6 papers between 2020 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
Gate-Level RTL Description of the Glitch Optimized Multipliers.
Dataset, May, 2022

Ultra-Low-Voltage Flip-Flops and Near-Threshold Modeling.
Dataset, January, 2022

2021
Novel Ultra-Low-Voltage Flip-Flops: Near-Vth Modeling and VLSI Integration.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020
Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Ultra-Low Voltage 4-to-2 Compressors for Near-Vth Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-$V_{th}$ Computing.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020


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