LV*: a class of lazy versioning HTMs for low-cost integration of transactional memory systems. - Anurag Negi; M. M. Waliullah; Per Stenström (IFMT, 2010)

LV*: A low complexity lazy versioning HTM infrastructure. - Anurag Negi; M. M. Waliullah; Per Stenström (ICSAMOS, 2010)

Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. - Anurag Negi; Per Stenström; J. Rubén Titos Gil; Manuel E. Acacio; José M. García 001 (PACT, 2011)

Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. - Anurag Negi; J. Rubén Titos Gil; Manuel E. Acacio; José M. García 001; Per Stenström (ICPP, 2011)

ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. - J. Rubén Titos Gil; Anurag Negi; Manuel E. Acacio; José M. García 001; Per Stenström (ICS, 2011)

The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. - Anurag Negi; J. Rubén Titos Gil; Manuel E. Acacio; José M. García 001; Per Stenström (IPDPS Workshops, 2011)

Transactional prefetching: narrowing the window of contention in hardware transactional memory. - Anurag Negi; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Per Stenström (PACT, 2012)

π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. - Anurag Negi; J. Rubén Titos Gil; Manuel E. Acacio; José M. García 001; Per Stenström (HPCA, 2012)

HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory. - Adrià Armejach; Anurag Negi; Adrián Cristal; Osman S. Unsal; Per Stenström; Tim Harris 001 (HiPC, 2013)

Efficient Forwarding of Producer-Consumer Data in Task-Based Programs. - Madhavan Manivannan; Anurag Negi; Per Stenström (ICPP, 2013)

Techniques to improve performance in requester-wins hardware transactional memory. - Adrià Armejach; J. Rubén Titos Gil; Anurag Negi; Osman S. Unsal; Adrián Cristal (ACM Trans. Archit. Code Optim., 2013)

SCIN-cache: Fast speculative versioning in multithreaded cores. - Anurag Negi; J. Rubén Titos Gil (ACM Trans. Archit. Code Optim., 2013)

Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory. - J. Rubén Titos Gil; Anurag Negi; Manuel E. Acacio; José M. García 001; Per Stenström (IEEE Trans. Parallel Distributed Syst., 2013)

Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell. - Bhavishya Goel; J. Rubén Titos Gil; Anurag Negi; Sally A. McKee; Per Stenström (IPDPS, 2014)

ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory. - J. Rubén Titos Gil; Anurag Negi; Manuel E. Acacio; José M. García 001; Per Stenström (IEEE Trans. Parallel Distributed Syst., 2014)